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linux-headers: Update to v3.10-rc5
This adds symbols required for PPC64 pseries platform features: 1. sPAPR live migration; 2. in-kernel XICS interrupt controller. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Alexey Kardashevskiy
Michael Tokarev
parent
8216966004
commit
e098b45386
8 changed files with 299 additions and 13 deletions
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@ -53,12 +53,12 @@
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#define KVM_ARM_FIQ_spsr fiq_regs[7]
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struct kvm_regs {
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struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */
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__u32 svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
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__u32 abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
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__u32 und_regs[3]; /* SP_und, LR_und, SPSR_und */
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__u32 irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
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__u32 fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
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struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
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unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
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unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
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unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
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unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
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unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
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};
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/* Supported Processor Types */
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138
linux-headers/asm-mips/kvm.h
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138
linux-headers/asm-mips/kvm.h
Normal file
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@ -0,0 +1,138 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2013 Cavium, Inc.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#ifndef __LINUX_KVM_MIPS_H
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#define __LINUX_KVM_MIPS_H
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#include <linux/types.h>
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/*
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* KVM MIPS specific structures and definitions.
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*
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* Some parts derived from the x86 version of this file.
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*/
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/*
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* for KVM_GET_REGS and KVM_SET_REGS
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*
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* If Config[AT] is zero (32-bit CPU), the register contents are
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* stored in the lower 32-bits of the struct kvm_regs fields and sign
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* extended to 64-bits.
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*/
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struct kvm_regs {
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/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
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__u64 gpr[32];
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__u64 hi;
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__u64 lo;
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__u64 pc;
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};
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/*
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* for KVM_GET_FPU and KVM_SET_FPU
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*
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* If Status[FR] is zero (32-bit FPU), the upper 32-bits of the FPRs
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* are zero filled.
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*/
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struct kvm_fpu {
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__u64 fpr[32];
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__u32 fir;
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__u32 fccr;
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__u32 fexr;
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__u32 fenr;
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__u32 fcsr;
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__u32 pad;
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};
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/*
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* For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access CP0
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* registers. The id field is broken down as follows:
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*
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* bits[2..0] - Register 'sel' index.
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* bits[7..3] - Register 'rd' index.
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* bits[15..8] - Must be zero.
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* bits[63..16] - 1 -> CP0 registers.
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*
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* Other sets registers may be added in the future. Each set would
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* have its own identifier in bits[63..16].
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*
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* The addr field of struct kvm_one_reg must point to an aligned
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* 64-bit wide location. For registers that are narrower than
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* 64-bits, the value is stored in the low order bits of the location,
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* and sign extended to 64-bits.
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*
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* The registers defined in struct kvm_regs are also accessible, the
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* id values for these are below.
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*/
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#define KVM_REG_MIPS_R0 0
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#define KVM_REG_MIPS_R1 1
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#define KVM_REG_MIPS_R2 2
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#define KVM_REG_MIPS_R3 3
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#define KVM_REG_MIPS_R4 4
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#define KVM_REG_MIPS_R5 5
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#define KVM_REG_MIPS_R6 6
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#define KVM_REG_MIPS_R7 7
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#define KVM_REG_MIPS_R8 8
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#define KVM_REG_MIPS_R9 9
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#define KVM_REG_MIPS_R10 10
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#define KVM_REG_MIPS_R11 11
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#define KVM_REG_MIPS_R12 12
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#define KVM_REG_MIPS_R13 13
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#define KVM_REG_MIPS_R14 14
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#define KVM_REG_MIPS_R15 15
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#define KVM_REG_MIPS_R16 16
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#define KVM_REG_MIPS_R17 17
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#define KVM_REG_MIPS_R18 18
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#define KVM_REG_MIPS_R19 19
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#define KVM_REG_MIPS_R20 20
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#define KVM_REG_MIPS_R21 21
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#define KVM_REG_MIPS_R22 22
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#define KVM_REG_MIPS_R23 23
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#define KVM_REG_MIPS_R24 24
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#define KVM_REG_MIPS_R25 25
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#define KVM_REG_MIPS_R26 26
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#define KVM_REG_MIPS_R27 27
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#define KVM_REG_MIPS_R28 28
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#define KVM_REG_MIPS_R29 29
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#define KVM_REG_MIPS_R30 30
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#define KVM_REG_MIPS_R31 31
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#define KVM_REG_MIPS_HI 32
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#define KVM_REG_MIPS_LO 33
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#define KVM_REG_MIPS_PC 34
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/*
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* KVM MIPS specific structures and definitions
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*
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*/
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struct kvm_debug_exit_arch {
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__u64 epc;
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};
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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/* dummy definition */
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struct kvm_sregs {
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};
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struct kvm_mips_interrupt {
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/* in */
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__u32 cpu;
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__u32 irq;
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};
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#endif /* __LINUX_KVM_MIPS_H */
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1
linux-headers/asm-mips/kvm_para.h
Normal file
1
linux-headers/asm-mips/kvm_para.h
Normal file
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@ -0,0 +1 @@
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#include <asm-generic/kvm_para.h>
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@ -25,6 +25,8 @@
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/* Select powerpc specific features in <linux/kvm.h> */
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#define __KVM_HAVE_SPAPR_TCE
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#define __KVM_HAVE_PPC_SMT
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#define __KVM_HAVE_IRQCHIP
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#define __KVM_HAVE_IRQ_LINE
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struct kvm_regs {
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__u64 pc;
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@ -272,8 +274,31 @@ struct kvm_debug_exit_arch {
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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struct {
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/* H/W breakpoint/watchpoint address */
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__u64 addr;
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/*
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* Type denotes h/w breakpoint, read watchpoint, write
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* watchpoint or watchpoint (both read and write).
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*/
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#define KVMPPC_DEBUG_NONE 0x0
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#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1)
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#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2)
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#define KVMPPC_DEBUG_WATCH_READ (1UL << 3)
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__u32 type;
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__u32 reserved;
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} bp[16];
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};
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/* Debug related defines */
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/*
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* kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
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* and upper 16 bits are architecture specific. Architecture specific defines
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* that ioctl is for setting hardware breakpoint or software breakpoint.
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*/
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#define KVM_GUESTDBG_USE_SW_BP 0x00010000
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#define KVM_GUESTDBG_USE_HW_BP 0x00020000
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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@ -299,6 +324,12 @@ struct kvm_allocate_rma {
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__u64 rma_size;
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};
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/* for KVM_CAP_PPC_RTAS */
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struct kvm_rtas_token_args {
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char name[120];
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__u64 token; /* Use a token of 0 to undefine a mapping */
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};
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struct kvm_book3e_206_tlb_entry {
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__u32 mas8;
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__u32 mas1;
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@ -359,6 +390,26 @@ struct kvm_get_htab_header {
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__u16 n_invalid;
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};
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/* Per-vcpu XICS interrupt controller state */
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#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
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#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */
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#define KVM_REG_PPC_ICP_CPPR_MASK 0xff
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#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */
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#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff
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#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */
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#define KVM_REG_PPC_ICP_MFRR_MASK 0xff
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#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */
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#define KVM_REG_PPC_ICP_PPRI_MASK 0xff
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/* Device control API: PPC-specific devices */
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#define KVM_DEV_MPIC_GRP_MISC 1
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#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
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#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */
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#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */
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/* One-Reg API: PPC-specific registers */
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#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
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#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
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#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
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@ -422,4 +473,42 @@ struct kvm_get_htab_header {
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#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
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#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
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#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
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/* Debugging: Special instruction for software breakpoint */
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#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
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/* MMU registers */
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#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
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#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
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#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
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#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
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#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
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#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
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#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
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/*
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* TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
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* KVM_CAP_SW_TLB ioctl
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*/
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#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
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#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
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#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
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#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
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#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
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#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
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#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
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#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
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#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
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/* PPC64 eXternal Interrupt Controller Specification */
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#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
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/* Layout of 64-bit source attribute values */
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#define KVM_XICS_DESTINATION_SHIFT 0
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#define KVM_XICS_DESTINATION_MASK 0xffffffffULL
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#define KVM_XICS_PRIORITY_SHIFT 32
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#define KVM_XICS_PRIORITY_MASK 0xff
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#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40)
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#define KVM_XICS_MASKED (1ULL << 41)
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#define KVM_XICS_PENDING (1ULL << 42)
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#endif /* __LINUX_KVM_POWERPC_H */
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@ -29,7 +29,6 @@
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#define __KVM_HAVE_PIT
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#define __KVM_HAVE_IOAPIC
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#define __KVM_HAVE_IRQ_LINE
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#define __KVM_HAVE_DEVICE_ASSIGNMENT
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#define __KVM_HAVE_MSI
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#define __KVM_HAVE_USER_NMI
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#define __KVM_HAVE_GUEST_DEBUG
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@ -561,9 +561,7 @@ struct kvm_ppc_smmu_info {
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#define KVM_CAP_MP_STATE 14
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#define KVM_CAP_COALESCED_MMIO 15
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#define KVM_CAP_SYNC_MMU 16 /* Changes to host mmap are reflected in guest */
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#ifdef __KVM_HAVE_DEVICE_ASSIGNMENT
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#define KVM_CAP_DEVICE_ASSIGNMENT 17
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#endif
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#define KVM_CAP_IOMMU 18
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#ifdef __KVM_HAVE_MSI
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#define KVM_CAP_DEVICE_MSI 20
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@ -579,13 +577,9 @@ struct kvm_ppc_smmu_info {
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#ifdef __KVM_HAVE_PIT
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#define KVM_CAP_REINJECT_CONTROL 24
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#endif
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#ifdef __KVM_HAVE_IOAPIC
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#define KVM_CAP_IRQ_ROUTING 25
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#endif
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#define KVM_CAP_IRQ_INJECT_STATUS 26
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#ifdef __KVM_HAVE_DEVICE_ASSIGNMENT
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#define KVM_CAP_DEVICE_DEASSIGNMENT 27
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#endif
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#ifdef __KVM_HAVE_MSIX
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#define KVM_CAP_DEVICE_MSIX 28
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#endif
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@ -668,6 +662,10 @@ struct kvm_ppc_smmu_info {
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#define KVM_CAP_PPC_EPR 86
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#define KVM_CAP_ARM_PSCI 87
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#define KVM_CAP_ARM_SET_DEVICE_ADDR 88
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#define KVM_CAP_DEVICE_CTRL 89
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#define KVM_CAP_IRQ_MPIC 90
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#define KVM_CAP_PPC_RTAS 91
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#define KVM_CAP_IRQ_XICS 92
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#ifdef KVM_CAP_IRQ_ROUTING
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@ -820,6 +818,28 @@ struct kvm_arm_device_addr {
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__u64 addr;
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};
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/*
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* Device control API, available with KVM_CAP_DEVICE_CTRL
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*/
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#define KVM_CREATE_DEVICE_TEST 1
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struct kvm_create_device {
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__u32 type; /* in: KVM_DEV_TYPE_xxx */
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__u32 fd; /* out: device handle */
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__u32 flags; /* in: KVM_CREATE_DEVICE_xxx */
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};
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struct kvm_device_attr {
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__u32 flags; /* no flags currently defined */
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__u32 group; /* device-defined */
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__u64 attr; /* group-defined */
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__u64 addr; /* userspace address of attr data */
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};
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#define KVM_DEV_TYPE_FSL_MPIC_20 1
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#define KVM_DEV_TYPE_FSL_MPIC_42 2
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#define KVM_DEV_TYPE_XICS 3
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/*
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* ioctls for VM fds
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*/
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@ -907,6 +927,16 @@ struct kvm_s390_ucas_mapping {
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#define KVM_PPC_GET_HTAB_FD _IOW(KVMIO, 0xaa, struct kvm_get_htab_fd)
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/* Available with KVM_CAP_ARM_SET_DEVICE_ADDR */
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#define KVM_ARM_SET_DEVICE_ADDR _IOW(KVMIO, 0xab, struct kvm_arm_device_addr)
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/* Available with KVM_CAP_PPC_RTAS */
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#define KVM_PPC_RTAS_DEFINE_TOKEN _IOW(KVMIO, 0xac, struct kvm_rtas_token_args)
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/* ioctl for vm fd */
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#define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device)
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/* ioctls for fds returned by KVM_CREATE_DEVICE */
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#define KVM_SET_DEVICE_ATTR _IOW(KVMIO, 0xe1, struct kvm_device_attr)
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#define KVM_GET_DEVICE_ATTR _IOW(KVMIO, 0xe2, struct kvm_device_attr)
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#define KVM_HAS_DEVICE_ATTR _IOW(KVMIO, 0xe3, struct kvm_device_attr)
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/*
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* ioctls for vcpu fds
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@ -319,6 +319,7 @@ enum {
|
|||
VFIO_PCI_INTX_IRQ_INDEX,
|
||||
VFIO_PCI_MSI_IRQ_INDEX,
|
||||
VFIO_PCI_MSIX_IRQ_INDEX,
|
||||
VFIO_PCI_ERR_IRQ_INDEX,
|
||||
VFIO_PCI_NUM_IRQS
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -127,4 +127,32 @@ struct vhost_memory {
|
|||
/* vhost-net should add virtio_net_hdr for RX, and strip for TX packets. */
|
||||
#define VHOST_NET_F_VIRTIO_NET_HDR 27
|
||||
|
||||
/* VHOST_SCSI specific definitions */
|
||||
|
||||
/*
|
||||
* Used by QEMU userspace to ensure a consistent vhost-scsi ABI.
|
||||
*
|
||||
* ABI Rev 0: July 2012 version starting point for v3.6-rc merge candidate +
|
||||
* RFC-v2 vhost-scsi userspace. Add GET_ABI_VERSION ioctl usage
|
||||
* ABI Rev 1: January 2013. Ignore vhost_tpgt filed in struct vhost_scsi_target.
|
||||
* All the targets under vhost_wwpn can be seen and used by guset.
|
||||
*/
|
||||
|
||||
#define VHOST_SCSI_ABI_VERSION 1
|
||||
|
||||
struct vhost_scsi_target {
|
||||
int abi_version;
|
||||
char vhost_wwpn[224]; /* TRANSPORT_IQN_LEN */
|
||||
unsigned short vhost_tpgt;
|
||||
unsigned short reserved;
|
||||
};
|
||||
|
||||
#define VHOST_SCSI_SET_ENDPOINT _IOW(VHOST_VIRTIO, 0x40, struct vhost_scsi_target)
|
||||
#define VHOST_SCSI_CLEAR_ENDPOINT _IOW(VHOST_VIRTIO, 0x41, struct vhost_scsi_target)
|
||||
/* Changing this breaks userspace. */
|
||||
#define VHOST_SCSI_GET_ABI_VERSION _IOW(VHOST_VIRTIO, 0x42, int)
|
||||
/* Set and get the events missed flag */
|
||||
#define VHOST_SCSI_SET_EVENTS_MISSED _IOW(VHOST_VIRTIO, 0x43, __u32)
|
||||
#define VHOST_SCSI_GET_EVENTS_MISSED _IOW(VHOST_VIRTIO, 0x44, __u32)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue