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target/arm: Enable FEAT_S2FWB for -cpu max
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the inherited CLIDR_EL1 value from the Cortex-A57 has them as 1). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
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@ -52,6 +52,7 @@ the following architecture extensions:
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- FEAT_RAS (Reliability, availability, and serviceability)
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- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
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- FEAT_RNG (Random number generator)
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- FEAT_S2FWB (Stage 2 forced Write-Back)
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- FEAT_SB (Speculation Barrier)
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- FEAT_SEL2 (Secure EL2)
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- FEAT_SHA1 (SHA1 instructions)
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@ -812,6 +812,7 @@ static void aarch64_max_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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uint64_t t;
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uint32_t u;
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if (kvm_enabled() || hvf_enabled()) {
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/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
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@ -842,6 +843,15 @@ static void aarch64_max_initfn(Object *obj)
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t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
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cpu->midr = t;
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/*
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* We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
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* are zero.
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*/
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u = cpu->clidr;
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u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
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u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
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cpu->clidr = u;
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t = cpu->isar.id_aa64isar0;
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t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
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@ -918,6 +928,7 @@ static void aarch64_max_initfn(Object *obj)
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t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
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t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
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t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
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t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
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t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
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t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
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cpu->isar.id_aa64mmfr2 = t;
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