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Add boot LoongArch elf kernel with FDT

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v2: Fix 'make check-tcg' fail.
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Merge tag 'pull-loongarch-20240429' of https://gitlab.com/gaosong/qemu into staging

Add boot LoongArch elf kernel with FDT

v2: Fix 'make check-tcg' fail.

# -----BEGIN PGP SIGNATURE-----
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# iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZi8F3AAKCRBAov/yOSY+
# 35VrBADb6f1mYNUTG5iDvKppvA8RG1TybxfXfgA+Z9vPkJqFkT6wt8J+JFwgh3UT
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# kS7slW6XsZgKpLLvUkFttPt3G4DUN29CscVgy4Ci0zrqyNjnsw==
# =ufbc
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 28 Apr 2024 07:28:44 PM PDT
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20240429' of https://gitlab.com/gaosong/qemu:
  hw/loongarch: Add cells missing from rtc node
  hw/loongarch: Add cells missing from uart node
  hw/loongarch: fdt remove unused irqchip node
  hw/loongarch: fdt adds pcie irq_map node
  hw/loongarch: fdt adds pch_msi Controller
  hw/loongarch: fdt adds pch_pic Controller
  hw/loongarch: fdt adds Extend I/O Interrupt Controller
  hw/loongarch: fdt adds cpu interrupt controller node
  hw/loongarch: Fix fdt memory node wrong 'reg'
  hw/loongarch: Init efi_fdt table
  hw/loongarch: Init efi_initrd table
  hw/loongarch: Init efi_boot_memmap table
  hw/loongarch: Init efi_system_table
  hw/loongarch: Add init_cmdline
  hw/loongarch: Add slave cpu boot_code
  hw/loongarch: Add load initrd
  hw/loongarch: Move boot functions to boot.c

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-04-30 07:16:56 -07:00
parent 2358f1b60f 841ef2c9df
commit de7e907d01
8 changed files with 670 additions and 162 deletions
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336
hw/loongarch/boot.c Normal file
View file

@ -0,0 +1,336 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* LoongArch boot helper functions.
*
* Copyright (c) 2023 Loongson Technology Corporation Limited
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "target/loongarch/cpu.h"
#include "hw/loongarch/virt.h"
#include "hw/loader.h"
#include "elf.h"
#include "qemu/error-report.h"
#include "sysemu/reset.h"
#include "sysemu/qtest.h"
ram_addr_t initrd_offset;
uint64_t initrd_size;
static const unsigned int slave_boot_code[] = {
/* Configure reset ebase. */
0x0400302c, /* csrwr $t0, LOONGARCH_CSR_EENTRY */
/* Disable interrupt. */
0x0380100c, /* ori $t0, $zero,0x4 */
0x04000180, /* csrxchg $zero, $t0, LOONGARCH_CSR_CRMD */
/* Clear mailbox. */
0x1400002d, /* lu12i.w $t1, 1(0x1) */
0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
0x06481da0, /* iocsrwr.d $zero, $t1 */
/* Enable IPI interrupt. */
0x1400002c, /* lu12i.w $t0, 1(0x1) */
0x0400118c, /* csrxchg $t0, $t0, LOONGARCH_CSR_ECFG */
0x02fffc0c, /* addi.d $t0, $r0,-1(0xfff) */
0x1400002d, /* lu12i.w $t1, 1(0x1) */
0x038011ad, /* ori $t1, $t1, CORE_EN_OFF */
0x064819ac, /* iocsrwr.w $t0, $t1 */
0x1400002d, /* lu12i.w $t1, 1(0x1) */
0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
/* Wait for wakeup <.L11>: */
0x06488000, /* idle 0x0 */
0x03400000, /* andi $zero, $zero, 0x0 */
0x064809ac, /* iocsrrd.w $t0, $t1 */
0x43fff59f, /* beqz $t0, -12(0x7ffff4) # 48 <.L11> */
/* Read and clear IPI interrupt. */
0x1400002d, /* lu12i.w $t1, 1(0x1) */
0x064809ac, /* iocsrrd.w $t0, $t1 */
0x1400002d, /* lu12i.w $t1, 1(0x1) */
0x038031ad, /* ori $t1, $t1, CORE_CLEAR_OFF */
0x064819ac, /* iocsrwr.w $t0, $t1 */
/* Disable IPI interrupt. */
0x1400002c, /* lu12i.w $t0, 1(0x1) */
0x04001180, /* csrxchg $zero, $t0, LOONGARCH_CSR_ECFG */
/* Read mail buf and jump to specified entry */
0x1400002d, /* lu12i.w $t1, 1(0x1) */
0x038081ad, /* ori $t1, $t1, CORE_BUF_20 */
0x06480dac, /* iocsrrd.d $t0, $t1 */
0x00150181, /* move $ra, $t0 */
0x4c000020, /* jirl $zero, $ra,0 */
};
static inline void *guidcpy(void *dst, const void *src)
{
return memcpy(dst, src, sizeof(efi_guid_t));
}
static void init_efi_boot_memmap(struct efi_system_table *systab,
void *p, void *start)
{
unsigned i;
struct efi_boot_memmap *boot_memmap = p;
efi_guid_t tbl_guid = LINUX_EFI_BOOT_MEMMAP_GUID;
/* efi_configuration_table 1 */
guidcpy(&systab->tables[0].guid, &tbl_guid);
systab->tables[0].table = (struct efi_configuration_table *)(p - start);
systab->nr_tables = 1;
boot_memmap->desc_size = sizeof(efi_memory_desc_t);
boot_memmap->desc_ver = 1;
boot_memmap->map_size = 0;
efi_memory_desc_t *map = p + sizeof(struct efi_boot_memmap);
for (i = 0; i < memmap_entries; i++) {
map = (void *)boot_memmap + sizeof(*map);
map[i].type = memmap_table[i].type;
map[i].phys_addr = ROUND_UP(memmap_table[i].address, 64 * KiB);
map[i].num_pages = ROUND_DOWN(memmap_table[i].address +
memmap_table[i].length - map[i].phys_addr, 64 * KiB);
p += sizeof(efi_memory_desc_t);
}
}
static void init_efi_initrd_table(struct efi_system_table *systab,
void *p, void *start)
{
efi_guid_t tbl_guid = LINUX_EFI_INITRD_MEDIA_GUID;
struct efi_initrd *initrd_table = p;
/* efi_configuration_table 2 */
guidcpy(&systab->tables[1].guid, &tbl_guid);
systab->tables[1].table = (struct efi_configuration_table *)(p - start);
systab->nr_tables = 2;
initrd_table->base = initrd_offset;
initrd_table->size = initrd_size;
}
static void init_efi_fdt_table(struct efi_system_table *systab)
{
efi_guid_t tbl_guid = DEVICE_TREE_GUID;
/* efi_configuration_table 3 */
guidcpy(&systab->tables[2].guid, &tbl_guid);
systab->tables[2].table = (void *)FDT_BASE;
systab->nr_tables = 3;
}
static void init_systab(struct loongarch_boot_info *info, void *p, void *start)
{
void *bp_tables_start;
struct efi_system_table *systab = p;
info->a2 = p - start;
systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
systab->hdr.revision = EFI_SPECIFICATION_VERSION;
systab->hdr.revision = sizeof(struct efi_system_table),
systab->fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8;
systab->runtime = 0;
systab->boottime = 0;
systab->nr_tables = 0;
p += ROUND_UP(sizeof(struct efi_system_table), 64 * KiB);
systab->tables = p;
bp_tables_start = p;
init_efi_boot_memmap(systab, p, start);
p += ROUND_UP(sizeof(struct efi_boot_memmap) +
sizeof(efi_memory_desc_t) * memmap_entries, 64 * KiB);
init_efi_initrd_table(systab, p, start);
p += ROUND_UP(sizeof(struct efi_initrd), 64 * KiB);
init_efi_fdt_table(systab);
systab->tables = (struct efi_configuration_table *)(bp_tables_start - start);
}
static void init_cmdline(struct loongarch_boot_info *info, void *p, void *start)
{
hwaddr cmdline_addr = p - start;
info->a0 = 1;
info->a1 = cmdline_addr;
memcpy(p, info->kernel_cmdline, COMMAND_LINE_SIZE);
}
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
{
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
}
static int64_t load_kernel_info(struct loongarch_boot_info *info)
{
uint64_t kernel_entry, kernel_low, kernel_high;
ssize_t kernel_size;
kernel_size = load_elf(info->kernel_filename, NULL,
cpu_loongarch_virt_to_phys, NULL,
&kernel_entry, &kernel_low,
&kernel_high, NULL, 0,
EM_LOONGARCH, 1, 0);
if (kernel_size < 0) {
error_report("could not load kernel '%s': %s",
info->kernel_filename,
load_elf_strerror(kernel_size));
exit(1);
}
if (info->initrd_filename) {
initrd_size = get_image_size(info->initrd_filename);
if (initrd_size > 0) {
initrd_offset = ROUND_UP(kernel_high + 4 * kernel_size, 64 * KiB);
if (initrd_offset + initrd_size > info->ram_size) {
error_report("memory too small for initial ram disk '%s'",
info->initrd_filename);
exit(1);
}
initrd_size = load_image_targphys(info->initrd_filename, initrd_offset,
info->ram_size - initrd_offset);
}
if (initrd_size == (target_ulong)-1) {
error_report("could not load initial ram disk '%s'",
info->initrd_filename);
exit(1);
}
} else {
initrd_size = 0;
}
return kernel_entry;
}
static void reset_load_elf(void *opaque)
{
LoongArchCPU *cpu = opaque;
CPULoongArchState *env = &cpu->env;
cpu_reset(CPU(cpu));
if (env->load_elf) {
if (cpu == LOONGARCH_CPU(first_cpu)) {
env->gpr[4] = env->boot_info->a0;
env->gpr[5] = env->boot_info->a1;
env->gpr[6] = env->boot_info->a2;
}
cpu_set_pc(CPU(cpu), env->elf_address);
}
}
static void fw_cfg_add_kernel_info(struct loongarch_boot_info *info,
FWCfgState *fw_cfg)
{
/*
* Expose the kernel, the command line, and the initrd in fw_cfg.
* We don't process them here at all, it's all left to the
* firmware.
*/
load_image_to_fw_cfg(fw_cfg,
FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
info->kernel_filename,
false);
if (info->initrd_filename) {
load_image_to_fw_cfg(fw_cfg,
FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
info->initrd_filename, false);
}
if (info->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(info->kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
info->kernel_cmdline);
}
}
static void loongarch_firmware_boot(LoongArchMachineState *lams,
struct loongarch_boot_info *info)
{
fw_cfg_add_kernel_info(info, lams->fw_cfg);
}
static void init_boot_rom(struct loongarch_boot_info *info, void *p)
{
void *start = p;
init_cmdline(info, p, start);
p += COMMAND_LINE_SIZE;
init_systab(info, p, start);
}
static void loongarch_direct_kernel_boot(struct loongarch_boot_info *info)
{
void *p, *bp;
int64_t kernel_addr = 0;
LoongArchCPU *lacpu;
CPUState *cs;
if (info->kernel_filename) {
kernel_addr = load_kernel_info(info);
} else {
if(!qtest_enabled()) {
error_report("Need kernel filename\n");
exit(1);
}
}
/* Load cmdline and system tables at [0 - 1 MiB] */
p = g_malloc0(1 * MiB);
bp = p;
init_boot_rom(info, p);
rom_add_blob_fixed_as("boot_info", bp, 1 * MiB, 0, &address_space_memory);
/* Load slave boot code at pflash0 . */
void *boot_code = g_malloc0(VIRT_FLASH0_SIZE);
memcpy(boot_code, &slave_boot_code, sizeof(slave_boot_code));
rom_add_blob_fixed("boot_code", boot_code, VIRT_FLASH0_SIZE, VIRT_FLASH0_BASE);
CPU_FOREACH(cs) {
lacpu = LOONGARCH_CPU(cs);
lacpu->env.load_elf = true;
if (cs == first_cpu) {
lacpu->env.elf_address = kernel_addr;
} else {
lacpu->env.elf_address = VIRT_FLASH0_BASE;
}
lacpu->env.boot_info = info;
}
g_free(boot_code);
g_free(bp);
}
void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info)
{
LoongArchMachineState *lams = LOONGARCH_MACHINE(ms);
int i;
/* register reset function */
for (i = 0; i < ms->smp.cpus; i++) {
qemu_register_reset(reset_load_elf, LOONGARCH_CPU(qemu_get_cpu(i)));
}
info->kernel_filename = ms->kernel_filename;
info->kernel_cmdline = ms->kernel_cmdline;
info->initrd_filename = ms->initrd_filename;
if (lams->bios_loaded) {
loongarch_firmware_boot(lams, info);
} else {
loongarch_direct_kernel_boot(info);
}
}

1
hw/loongarch/meson.build
View file

@ -1,6 +1,7 @@
loongarch_ss = ss.source_set()
loongarch_ss.add(files(
'fw_cfg.c',
'boot.c',
))
loongarch_ss.add(when: 'CONFIG_LOONGARCH_VIRT', if_true: [files('virt.c'), fdt])
loongarch_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-build.c'))

365
hw/loongarch/virt.c
View file

@ -46,14 +46,6 @@
#include "hw/block/flash.h"
#include "qemu/error-report.h"
struct loaderparams {
uint64_t ram_size;
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
};
static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams,
const char *name,
const char *alias_prop_name)
@ -114,6 +106,101 @@ static void virt_flash_map(LoongArchMachineState *lams,
virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem);
}
static void fdt_add_cpuic_node(LoongArchMachineState *lams,
uint32_t *cpuintc_phandle)
{
MachineState *ms = MACHINE(lams);
char *nodename;
*cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
nodename = g_strdup_printf("/cpuic");
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle);
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
"loongson,cpu-interrupt-controller");
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
g_free(nodename);
}
static void fdt_add_eiointc_node(LoongArchMachineState *lams,
uint32_t *cpuintc_phandle,
uint32_t *eiointc_phandle)
{
MachineState *ms = MACHINE(lams);
char *nodename;
hwaddr extioi_base = APIC_BASE;
hwaddr extioi_size = EXTIOI_SIZE;
*eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt);
nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base);
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle);
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
"loongson,ls2k2000-eiointc");
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
*cpuintc_phandle);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3);
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0,
extioi_base, 0x0, extioi_size);
g_free(nodename);
}
static void fdt_add_pch_pic_node(LoongArchMachineState *lams,
uint32_t *eiointc_phandle,
uint32_t *pch_pic_phandle)
{
MachineState *ms = MACHINE(lams);
char *nodename;
hwaddr pch_pic_base = VIRT_PCH_REG_BASE;
hwaddr pch_pic_size = VIRT_PCH_REG_SIZE;
*pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base);
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle);
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
"loongson,pch-pic-1.0");
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0,
pch_pic_base, 0, pch_pic_size);
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
*eiointc_phandle);
qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0);
g_free(nodename);
}
static void fdt_add_pch_msi_node(LoongArchMachineState *lams,
uint32_t *eiointc_phandle,
uint32_t *pch_msi_phandle)
{
MachineState *ms = MACHINE(lams);
char *nodename;
hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW;
hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE;
*pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base);
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle);
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
"loongson,pch-msi-1.0");
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg",
0, pch_msi_base,
0, pch_msi_size);
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
*eiointc_phandle);
qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec",
VIRT_PCH_PIC_IRQ_NUM);
qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs",
EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM);
g_free(nodename);
}
static void fdt_add_flash_node(LoongArchMachineState *lams)
{
MachineState *ms = MACHINE(lams);
@ -144,7 +231,8 @@ static void fdt_add_flash_node(LoongArchMachineState *lams)
g_free(nodename);
}
static void fdt_add_rtc_node(LoongArchMachineState *lams)
static void fdt_add_rtc_node(LoongArchMachineState *lams,
uint32_t *pch_pic_phandle)
{
char *nodename;
hwaddr base = VIRT_RTC_REG_BASE;
@ -153,12 +241,18 @@ static void fdt_add_rtc_node(LoongArchMachineState *lams)
nodename = g_strdup_printf("/rtc@%" PRIx64, base);
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
"loongson,ls7a-rtc");
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
*pch_pic_phandle);
g_free(nodename);
}
static void fdt_add_uart_node(LoongArchMachineState *lams)
static void fdt_add_uart_node(LoongArchMachineState *lams,
uint32_t *pch_pic_phandle)
{
char *nodename;
hwaddr base = VIRT_UART_BASE;
@ -171,6 +265,10 @@ static void fdt_add_uart_node(LoongArchMachineState *lams)
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
*pch_pic_phandle);
g_free(nodename);
}
@ -265,7 +363,62 @@ static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams)
g_free(nodename);
}
static void fdt_add_pcie_node(const LoongArchMachineState *lams)
static void fdt_add_pcie_irq_map_node(const LoongArchMachineState *lams,
char *nodename,
uint32_t *pch_pic_phandle)
{
int pin, dev;
uint32_t irq_map_stride = 0;
uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {};
uint32_t *irq_map = full_irq_map;
const MachineState *ms = MACHINE(lams);
/* This code creates a standard swizzle of interrupts such that
* each device's first interrupt is based on it's PCI_SLOT number.
* (See pci_swizzle_map_irq_fn())
*
* We only need one entry per interrupt in the table (not one per
* possible slot) seeing the interrupt-map-mask will allow the table
* to wrap to any number of devices.
*/
for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
int devfn = dev * 0x8;
for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
int i = 0;
/* Fill PCI address cells */
irq_map[i] = cpu_to_be32(devfn << 8);
i += 3;
/* Fill PCI Interrupt cells */
irq_map[i] = cpu_to_be32(pin + 1);
i += 1;
/* Fill interrupt controller phandle and cells */
irq_map[i++] = cpu_to_be32(*pch_pic_phandle);
irq_map[i++] = cpu_to_be32(irq_nr);
if (!irq_map_stride) {
irq_map_stride = i;
}
irq_map += irq_map_stride;
}
}
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map,
GPEX_NUM_IRQS * GPEX_NUM_IRQS *
irq_map_stride * sizeof(uint32_t));
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
0x1800, 0, 0, 0x7);
}
static void fdt_add_pcie_node(const LoongArchMachineState *lams,
uint32_t *pch_pic_phandle,
uint32_t *pch_msi_phandle)
{
char *nodename;
hwaddr base_mmio = VIRT_PCI_MEM_BASE;
@ -296,34 +449,11 @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
2, base_pio, 2, size_pio,
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
2, base_mmio, 2, size_mmio);
g_free(nodename);
}
qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
0, *pch_msi_phandle, 0, 0x10000);
static void fdt_add_irqchip_node(LoongArchMachineState *lams)
{
MachineState *ms = MACHINE(lams);
char *nodename;
uint32_t irqchip_phandle;
fdt_add_pcie_irq_map_node(lams, nodename, pch_pic_phandle);
irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt);
qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle);
nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE);
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
"loongarch,ls7a");
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
2, VIRT_IOAPIC_REG_BASE,
2, PCH_PIC_ROUTE_ENTRY_OFFSET);
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle);
g_free(nodename);
}
@ -333,7 +463,7 @@ static void fdt_add_memory_node(MachineState *ms,
char *nodename = g_strdup_printf("/memory@%" PRIx64, base);
qemu_fdt_add_subnode(ms->fdt, nodename);
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, 0, size);
qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
if (ms->numa_state && ms->numa_state->num_nodes) {
@ -386,15 +516,8 @@ static void virt_powerdown_req(Notifier *notifier, void *opaque)
acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS);
}
struct memmap_entry {
uint64_t address;
uint64_t length;
uint32_t type;
uint32_t reserved;
};
static struct memmap_entry *memmap_table;
static unsigned memmap_entries;
struct memmap_entry *memmap_table;
unsigned memmap_entries;
static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
{
@ -412,31 +535,6 @@ static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
memmap_entries++;
}
static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
{
return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS);
}
static int64_t load_kernel_info(const struct loaderparams *loaderparams)
{
uint64_t kernel_entry, kernel_low, kernel_high;
ssize_t kernel_size;
kernel_size = load_elf(loaderparams->kernel_filename, NULL,
cpu_loongarch_virt_to_phys, NULL,
&kernel_entry, &kernel_low,
&kernel_high, NULL, 0,
EM_LOONGARCH, 1, 0);
if (kernel_size < 0) {
error_report("could not load kernel '%s': %s",
loaderparams->kernel_filename,
load_elf_strerror(kernel_size));
exit(1);
}
return kernel_entry;
}
static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams)
{
DeviceState *dev;
@ -487,7 +585,10 @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
return dev;
}
static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams)
static void loongarch_devices_init(DeviceState *pch_pic,
LoongArchMachineState *lams,
uint32_t *pch_pic_phandle,
uint32_t *pch_msi_phandle)
{
MachineClass *mc = MACHINE_GET_CLASS(lams);
DeviceState *gpex_dev;
@ -533,11 +634,14 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
}
/* Add pcie node */
fdt_add_pcie_node(lams, pch_pic_phandle, pch_msi_phandle);
serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,
qdev_get_gpio_in(pch_pic,
VIRT_UART_IRQ - VIRT_GSI_BASE),
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
fdt_add_uart_node(lams);
fdt_add_uart_node(lams, pch_pic_phandle);
/* Network init */
pci_init_nic_devices(pci_bus, mc->default_nic);
@ -550,7 +654,7 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
qdev_get_gpio_in(pch_pic,
VIRT_RTC_IRQ - VIRT_GSI_BASE));
fdt_add_rtc_node(lams);
fdt_add_rtc_node(lams, pch_pic_phandle);
/* acpi ged */
lams->acpi_ged = create_acpi_ged(pch_pic, lams);
@ -568,6 +672,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
CPULoongArchState *env;
CPUState *cpu_state;
int cpu, pin, i, start, num;
uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
/*
* The connection of interrupts:
@ -602,6 +707,9 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR,
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
/* Add cpu interrupt-controller */
fdt_add_cpuic_node(lams, &cpuintc_phandle);
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
cpu_state = qemu_get_cpu(cpu);
cpudev = DEVICE(cpu_state);
@ -633,6 +741,9 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
}
}
/* Add Extend I/O Interrupt Controller node */
fdt_add_eiointc_node(lams, &cpuintc_phandle, &eiointc_phandle);
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
num = VIRT_PCH_PIC_IRQ_NUM;
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
@ -652,6 +763,9 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
}
/* Add PCH PIC node */
fdt_add_pch_pic_node(lams, &eiointc_phandle, &pch_pic_phandle);
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
start = num;
num = EXTIOI_IRQS - start;
@ -666,7 +780,10 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
qdev_get_gpio_in(extioi, i + start));
}
loongarch_devices_init(pch_pic, lams);
/* Add PCH MSI node */
fdt_add_pch_msi_node(lams, &eiointc_phandle, &pch_msi_phandle);
loongarch_devices_init(pch_pic, lams, &pch_pic_phandle, &pch_msi_phandle);
}
static void loongarch_firmware_init(LoongArchMachineState *lams)
@ -717,67 +834,6 @@ static void loongarch_firmware_init(LoongArchMachineState *lams)
}
}
static void reset_load_elf(void *opaque)
{
LoongArchCPU *cpu = opaque;
CPULoongArchState *env = &cpu->env;
cpu_reset(CPU(cpu));
if (env->load_elf) {
cpu_set_pc(CPU(cpu), env->elf_address);
}
}
static void fw_cfg_add_kernel_info(const struct loaderparams *loaderparams,
FWCfgState *fw_cfg)
{
/*
* Expose the kernel, the command line, and the initrd in fw_cfg.
* We don't process them here at all, it's all left to the
* firmware.
*/
load_image_to_fw_cfg(fw_cfg,
FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
loaderparams->kernel_filename,
false);
if (loaderparams->initrd_filename) {
load_image_to_fw_cfg(fw_cfg,
FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
loaderparams->initrd_filename, false);
}
if (loaderparams->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(loaderparams->kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
loaderparams->kernel_cmdline);
}
}
static void loongarch_firmware_boot(LoongArchMachineState *lams,
const struct loaderparams *loaderparams)
{
fw_cfg_add_kernel_info(loaderparams, lams->fw_cfg);
}
static void loongarch_direct_kernel_boot(LoongArchMachineState *lams,
const struct loaderparams *loaderparams)
{
MachineState *machine = MACHINE(lams);
int64_t kernel_addr = 0;
LoongArchCPU *lacpu;
int i;
kernel_addr = load_kernel_info(loaderparams);
if (!machine->firmware) {
for (i = 0; i < machine->smp.cpus; i++) {
lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
lacpu->env.load_elf = true;
lacpu->env.elf_address = kernel_addr;
}
}
}
static void loongarch_qemu_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
@ -828,12 +884,10 @@ static void loongarch_init(MachineState *machine)
int nb_numa_nodes = machine->numa_state->num_nodes;
NodeInfo *numa_info = machine->numa_state->nodes;
int i;
hwaddr fdt_base;
const CPUArchIdList *possible_cpus;
MachineClass *mc = MACHINE_GET_CLASS(machine);
CPUState *cpu;
char *ramName = NULL;
struct loaderparams loaderparams = { };
if (!cpu_model) {
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@ -936,28 +990,11 @@ static void loongarch_init(MachineState *machine)
sizeof(struct memmap_entry) * (memmap_entries));
}
fdt_add_fw_cfg_node(lams);
loaderparams.ram_size = ram_size;
loaderparams.kernel_filename = machine->kernel_filename;
loaderparams.kernel_cmdline = machine->kernel_cmdline;
loaderparams.initrd_filename = machine->initrd_filename;
/* load the kernel. */
if (loaderparams.kernel_filename) {
if (lams->bios_loaded) {
loongarch_firmware_boot(lams, &loaderparams);
} else {
loongarch_direct_kernel_boot(lams, &loaderparams);
}
}
fdt_add_flash_node(lams);
/* register reset function */
for (i = 0; i < machine->smp.cpus; i++) {
lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
qemu_register_reset(reset_load_elf, lacpu);
}
/* Initialize the IO interrupt subsystem */
loongarch_irq_init(lams);
fdt_add_irqchip_node(lams);
platform_bus_add_all_fdt_nodes(machine->fdt, "/intc",
platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
VIRT_PLATFORM_BUS_BASEADDRESS,
VIRT_PLATFORM_BUS_SIZE,
VIRT_PLATFORM_BUS_IRQ);
@ -967,7 +1004,6 @@ static void loongarch_init(MachineState *machine)
lams->powerdown_notifier.notify = virt_powerdown_req;
qemu_register_powerdown_notifier(&lams->powerdown_notifier);
fdt_add_pcie_node(lams);
/*
* Since lowmem region starts from 0 and Linux kernel legacy start address
* at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
@ -975,9 +1011,14 @@ static void loongarch_init(MachineState *machine)
* Put the FDT into the memory map as a ROM image: this will ensure
* the FDT is copied again upon reset, even if addr points into RAM.
*/
fdt_base = 1 * MiB;
qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
rom_add_blob_fixed_as("fdt", machine->fdt, lams->fdt_size, FDT_BASE,
&address_space_memory);
qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
rom_ptr_for_as(&address_space_memory, FDT_BASE, lams->fdt_size));
lams->bootinfo.ram_size = ram_size;
loongarch_load_kernel(machine, &lams->bootinfo);
}
bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)

1
include/hw/intc/loongarch_extioi.h
View file

@ -39,6 +39,7 @@
#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
#define EXTIOI_SIZE 0x800
typedef struct ExtIOICore {
uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];

109
include/hw/loongarch/boot.h Normal file
View file

@ -0,0 +1,109 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Definitions for LoongArch boot.
*
* Copyright (C) 2023 Loongson Technology Corporation Limited
*/
#ifndef HW_LOONGARCH_BOOT_H
#define HW_LOONGARCH_BOOT_H
/* UEFI 2.10 */
#define EFI_SYSTEM_TABLE_SIGNATURE 0x5453595320494249
#define EFI_2_100_SYSTEM_TABLE_REVISION ((2<<16) | (100))
#define EFI_SPECIFICATION_VERSION EFI_SYSTEM_TABLE_REVISION
#define EFI_SYSTEM_TABLE_REVISION EFI_2_100_SYSTEM_TABLE_REVISION
#define FW_VERSION 0x1
#define FW_PATCHLEVEL 0x0
typedef struct {
uint8_t b[16];
} efi_guid_t QEMU_ALIGNED(8);
#define EFI_GUID(a, b, c, d...) (efi_guid_t){ { \
(a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
(b) & 0xff, ((b) >> 8) & 0xff, \
(c) & 0xff, ((c) >> 8) & 0xff, d } }
#define LINUX_EFI_BOOT_MEMMAP_GUID \
EFI_GUID(0x800f683f, 0xd08b, 0x423a, 0xa2, 0x93, \
0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4)
#define LINUX_EFI_INITRD_MEDIA_GUID \
EFI_GUID(0x5568e427, 0x68fc, 0x4f3d, 0xac, 0x74, \
0xca, 0x55, 0x52, 0x31, 0xcc, 0x68)
#define DEVICE_TREE_GUID \
EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, 0x83, 0x0b, \
0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
struct efi_config_table {
efi_guid_t guid;
uint64_t *ptr;
const char name[16];
};
typedef struct {
uint64_t signature;
uint32_t revision;
uint32_t headersize;
uint32_t crc32;
uint32_t reserved;
} efi_table_hdr_t;
struct efi_configuration_table {
efi_guid_t guid;
void *table;
};
struct efi_system_table {
efi_table_hdr_t hdr;
uint64_t fw_vendor; /* physical addr of CHAR16 vendor string */
uint32_t fw_revision;
uint64_t con_in_handle;
uint64_t *con_in;
uint64_t con_out_handle;
uint64_t *con_out;
uint64_t stderr_handle;
uint64_t stderr_placeholder;
uint64_t *runtime;
uint64_t *boottime;
uint64_t nr_tables;
struct efi_configuration_table *tables;
};
typedef struct {
uint32_t type;
uint32_t pad;
uint64_t phys_addr;
uint64_t virt_addr;
uint64_t num_pages;
uint64_t attribute;
} efi_memory_desc_t;
struct efi_boot_memmap {
uint64_t map_size;
uint64_t desc_size;
uint32_t desc_ver;
uint64_t map_key;
uint64_t buff_size;
efi_memory_desc_t map[32];
};
struct efi_initrd {
uint64_t base;
uint64_t size;
};
struct loongarch_boot_info {
uint64_t ram_size;
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
uint64_t a0, a1, a2;
};
void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *info);
#endif /* HW_LOONGARCH_BOOT_H */

16
include/hw/loongarch/virt.h
View file

@ -13,6 +13,7 @@
#include "qemu/queue.h"
#include "hw/intc/loongarch_ipi.h"
#include "hw/block/flash.h"
#include "hw/loongarch/boot.h"
#define LOONGARCH_MAX_CPUS 256
@ -32,6 +33,20 @@
#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
#define COMMAND_LINE_SIZE 512
#define FDT_BASE 0x100000
extern struct memmap_entry *memmap_table;
extern unsigned memmap_entries;
struct memmap_entry {
uint64_t address;
uint64_t length;
uint32_t type;
uint32_t reserved;
};
struct LoongArchMachineState {
/*< private >*/
MachineState parent_obj;
@ -55,6 +70,7 @@ struct LoongArchMachineState {
MemoryRegion system_iocsr;
MemoryRegion iocsr_mem;
AddressSpace as_iocsr;
struct loongarch_boot_info bootinfo;
};
#define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt")

2
include/hw/pci-host/ls7a.h
View file

@ -24,6 +24,8 @@
#define VIRT_PCH_REG_BASE 0x10000000UL
#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
#define VIRT_PCH_REG_SIZE 0x400
#define VIRT_PCH_MSI_SIZE 0x8
/*
* GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot

2
target/loongarch/cpu.h
View file

@ -359,6 +359,8 @@ typedef struct CPUArchState {
uint32_t mp_state;
/* Store ipistate to access from this struct */
DeviceState *ipistate;
struct loongarch_boot_info *boot_info;
#endif
} CPULoongArchState;