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hw/arm/xilinx_zynq: Support up to two CPU cores

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The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only
one core).  Add support for up to two simulated cores.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Message-id: 20240524120837.10057-3-sebastian.huber@embedded-brains.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: removed unnecessary double-cast]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Sebastian Huber 2024-05-24 14:08:37 +02:00 committed by Peter Maydell
parent f271877307
commit ddcf58e044
1 changed files with 33 additions and 21 deletions
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54
hw/arm/xilinx_zynq.c
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@ -84,9 +84,12 @@ static const int dma_irqs[8] = {
0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
0xe5801000 + (addr)
#define ZYNQ_MAX_CPUS 2
struct ZynqMachineState {
MachineState parent;
Clock *ps_clk;
ARMCPU *cpu[ZYNQ_MAX_CPUS];
};
static void zynq_write_board_setup(ARMCPU *cpu,
@ -176,13 +179,13 @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
static void zynq_init(MachineState *machine)
{
ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
ARMCPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
DeviceState *dev, *slcr;
SysBusDevice *busdev;
qemu_irq pic[64];
int n;
unsigned int smp_cpus = machine->smp.cpus;
/* max 2GB ram */
if (machine->ram_size > 2 * GiB) {
@ -190,22 +193,27 @@ static void zynq_init(MachineState *machine)
exit(EXIT_FAILURE);
}
cpu = ARM_CPU(object_new(machine->cpu_type));
for (n = 0; n < smp_cpus; n++) {
Object *cpuobj = object_new(machine->cpu_type);
/* By default A9 CPUs have EL3 enabled. This board does not
* currently support EL3 so the CPU EL3 property is disabled before
* realization.
*/
if (object_property_find(OBJECT(cpu), "has_el3")) {
object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal);
/*
* By default A9 CPUs have EL3 enabled. This board does not currently
* support EL3 so the CPU EL3 property is disabled before realization.
*/
if (object_property_find(cpuobj, "has_el3")) {
object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
}
object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR,
&error_fatal);
object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
&error_fatal);
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
zynq_machine->cpu[n] = ARM_CPU(cpuobj);
}
object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR,
&error_fatal);
object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE,
&error_fatal);
qdev_realize(DEVICE(cpu), NULL, &error_fatal);
/* DDR remapped to address zero. */
memory_region_add_subregion(address_space_mem, 0, machine->ram);
@ -237,15 +245,19 @@ static void zynq_init(MachineState *machine)
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", 1);
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
sysbus_connect_irq(busdev, 1,
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
for (n = 0; n < smp_cpus; n++) {
DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]);
sysbus_connect_irq(busdev, (2 * n) + 0,
qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(busdev, (2 * n) + 1,
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
}
for (n = 0; n < 64; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
@ -350,7 +362,7 @@ static void zynq_init(MachineState *machine)
zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
zynq_binfo.write_board_setup = zynq_write_board_setup;
arm_load_kernel(cpu, machine, &zynq_binfo);
arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo);
}
static void zynq_machine_class_init(ObjectClass *oc, void *data)
@ -362,7 +374,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
mc->init = zynq_init;
mc->max_cpus = 1;
mc->max_cpus = ZYNQ_MAX_CPUS;
mc->no_sdcard = 1;
mc->ignore_memory_transaction_failures = true;
mc->valid_cpu_types = valid_cpu_types;