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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
We now have the address size as part of the opcode, so we no longer need to test TARGET_LONG_BITS. We can use uint64_t for target_ulong, as passed into load/store helpers. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
fecccfcc54
commit
dd7dc93ef0
61
tcg/tci.c
61
tcg/tci.c
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@ -286,7 +286,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
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return result;
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}
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static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
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static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr,
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MemOpIdx oi, const void *tb_ptr)
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{
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MemOp mop = get_memop(oi);
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@ -312,7 +312,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
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}
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}
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static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
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static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val,
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MemOpIdx oi, const void *tb_ptr)
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{
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MemOp mop = get_memop(oi);
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@ -372,10 +372,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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TCGReg r0, r1, r2, r3, r4, r5;
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tcg_target_ulong t1;
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TCGCond condition;
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target_ulong taddr;
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uint8_t pos, len;
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uint32_t tmp32;
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uint64_t tmp64;
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uint64_t tmp64, taddr;
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uint64_t T1, T2;
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MemOpIdx oi;
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int32_t ofs;
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@ -923,31 +922,40 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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break;
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case INDEX_op_qemu_ld_a32_i32:
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tci_args_rrm(insn, &r0, &r1, &oi);
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taddr = (uint32_t)regs[r1];
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goto do_ld_i32;
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case INDEX_op_qemu_ld_a64_i32:
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if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
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if (TCG_TARGET_REG_BITS == 64) {
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tci_args_rrm(insn, &r0, &r1, &oi);
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taddr = regs[r1];
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} else {
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tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
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taddr = tci_uint64(regs[r2], regs[r1]);
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}
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tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
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regs[r0] = tmp32;
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do_ld_i32:
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regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr);
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break;
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case INDEX_op_qemu_ld_a32_i64:
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if (TCG_TARGET_REG_BITS == 64) {
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tci_args_rrm(insn, &r0, &r1, &oi);
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taddr = (uint32_t)regs[r1];
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} else {
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tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
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taddr = (uint32_t)regs[r2];
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}
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goto do_ld_i64;
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case INDEX_op_qemu_ld_a64_i64:
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if (TCG_TARGET_REG_BITS == 64) {
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tci_args_rrm(insn, &r0, &r1, &oi);
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taddr = regs[r1];
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} else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
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tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
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taddr = regs[r2];
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} else {
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tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
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taddr = tci_uint64(regs[r3], regs[r2]);
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oi = regs[r4];
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}
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do_ld_i64:
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tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
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if (TCG_TARGET_REG_BITS == 32) {
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tci_write_reg64(regs, r1, r0, tmp64);
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@ -957,35 +965,44 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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break;
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case INDEX_op_qemu_st_a32_i32:
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tci_args_rrm(insn, &r0, &r1, &oi);
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taddr = (uint32_t)regs[r1];
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goto do_st_i32;
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case INDEX_op_qemu_st_a64_i32:
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if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
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if (TCG_TARGET_REG_BITS == 64) {
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tci_args_rrm(insn, &r0, &r1, &oi);
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taddr = regs[r1];
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} else {
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tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
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taddr = tci_uint64(regs[r2], regs[r1]);
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}
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tmp32 = regs[r0];
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tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
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do_st_i32:
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tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr);
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break;
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case INDEX_op_qemu_st_a32_i64:
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if (TCG_TARGET_REG_BITS == 64) {
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tci_args_rrm(insn, &r0, &r1, &oi);
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tmp64 = regs[r0];
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taddr = (uint32_t)regs[r1];
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} else {
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tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
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tmp64 = tci_uint64(regs[r1], regs[r0]);
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taddr = (uint32_t)regs[r2];
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}
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goto do_st_i64;
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case INDEX_op_qemu_st_a64_i64:
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if (TCG_TARGET_REG_BITS == 64) {
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tci_args_rrm(insn, &r0, &r1, &oi);
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taddr = regs[r1];
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tmp64 = regs[r0];
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taddr = regs[r1];
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} else {
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if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
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tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
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taddr = regs[r2];
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} else {
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tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
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taddr = tci_uint64(regs[r3], regs[r2]);
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oi = regs[r4];
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}
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tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4);
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tmp64 = tci_uint64(regs[r1], regs[r0]);
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taddr = tci_uint64(regs[r3], regs[r2]);
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oi = regs[r4];
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}
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do_st_i64:
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tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
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break;
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@ -243,7 +243,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
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return false;
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}
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static void stack_bounds_check(TCGReg base, target_long offset)
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static void stack_bounds_check(TCGReg base, intptr_t offset)
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{
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if (base == TCG_REG_CALL_STACK) {
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tcg_debug_assert(offset >= 0);
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@ -850,24 +850,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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break;
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case INDEX_op_qemu_ld_a32_i32:
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case INDEX_op_qemu_ld_a64_i32:
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case INDEX_op_qemu_st_a32_i32:
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tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
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break;
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case INDEX_op_qemu_ld_a64_i32:
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case INDEX_op_qemu_st_a64_i32:
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if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
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case INDEX_op_qemu_ld_a32_i64:
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case INDEX_op_qemu_st_a32_i64:
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
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} else {
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tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
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}
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break;
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case INDEX_op_qemu_ld_a32_i64:
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case INDEX_op_qemu_ld_a64_i64:
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case INDEX_op_qemu_st_a32_i64:
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case INDEX_op_qemu_st_a64_i64:
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_op_rrm(s, opc, args[0], args[1], args[2]);
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} else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) {
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tcg_out_op_rrrm(s, opc, args[0], args[1], args[2], args[3]);
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} else {
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, args[4]);
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tcg_out_op_rrrrr(s, opc, args[0], args[1],
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