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Delete unused tb_invalidate_page_range

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tb_invalidate_page_range() was intended to be used to invalidate an
area of a TB which the guest explicitly flushes from i-cache. However,
QEMU detects writes to code areas where TBs have been generated, so
his has never been useful.

Delete the function, adjust callers.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2011-05-14 11:55:30 +00:00
parent 1fddfba129
commit dcfd14b374
7 changed files with 3 additions and 43 deletions
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13
cpu-exec.c
View file

@ -704,19 +704,6 @@ int cpu_exec(CPUState *env1)
return ret;
}
/* must only be called from the generated code as an exception can be
generated */
void tb_invalidate_page_range(target_ulong start, target_ulong end)
{
/* XXX: cannot enable it yet because it yields to MMU exception
where NIP != read address on PowerPC */
#if 0
target_ulong phys_addr;
phys_addr = get_phys_addr_code(env, start);
tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
#endif
}
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)

1
exec-all.h
View file

@ -95,7 +95,6 @@ void QEMU_NORETURN cpu_loop_exit(void);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
#if !defined(CONFIG_USER_ONLY)

22
linux-user/main.c
View file

@ -455,24 +455,6 @@ void cpu_loop(CPUX86State *env)
#ifdef TARGET_ARM
static void arm_cache_flush(abi_ulong start, abi_ulong last)
{
abi_ulong addr, last1;
if (last < start)
return;
addr = start;
for(;;) {
last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
if (last1 > last)
last1 = last;
tb_invalidate_page_range(addr, last1 + 1);
if (last1 == last)
break;
addr = last1 + 1;
}
}
/* Handle a jump to the kernel code page. */
static int
do_kernel_trap(CPUARMState *env)
@ -717,7 +699,7 @@ void cpu_loop(CPUARMState *env)
}
if (n == ARM_NR_cacheflush) {
arm_cache_flush(env->regs[0], env->regs[1]);
/* nop */
} else if (n == ARM_NR_semihosting
|| n == ARM_NR_thumb_semihosting) {
env->regs[0] = do_arm_semihosting (env);
@ -733,7 +715,7 @@ void cpu_loop(CPUARMState *env)
if ( n > ARM_NR_BASE) {
switch (n) {
case ARM_NR_cacheflush:
arm_cache_flush(env->regs[0], env->regs[1]);
/* nop */
break;
case ARM_NR_set_tls:
cpu_set_tls(env, env->regs[0]);

1
target-ppc/op_helper.c
View file

@ -362,7 +362,6 @@ void helper_icbi(target_ulong addr)
* do the load "by hand".
*/
ldl(addr);
tb_invalidate_page_range(addr, addr + env->icache_line_size);
}
// XXX: to be tested

1
target-sparc/helper.h
View file

@ -35,7 +35,6 @@ DEF_HELPER_2(check_align, void, tl, i32)
DEF_HELPER_0(debug, void)
DEF_HELPER_0(save, void)
DEF_HELPER_0(restore, void)
DEF_HELPER_1(flush, void, tl)
DEF_HELPER_2(udiv, tl, tl, tl)
DEF_HELPER_2(udiv_cc, tl, tl, tl)
DEF_HELPER_2(sdiv, tl, tl, tl)

6
target-sparc/op_helper.c
View file

@ -4092,12 +4092,6 @@ void helper_write_softint(uint64_t value)
}
#endif
void helper_flush(target_ulong addr)
{
addr &= ~7;
tb_invalidate_page_range(addr, addr + 8);
}
#ifdef TARGET_SPARC64
#ifdef DEBUG_PCALL
static const char * const excp_names[0x80] = {

2
target-sparc/translate.c
View file

@ -4226,7 +4226,7 @@ static void disas_sparc_insn(DisasContext * dc)
case 0x3b: /* flush */
if (!((dc)->def->features & CPU_FEATURE_FLUSH))
goto unimp_flush;
gen_helper_flush(cpu_dst);
/* nop */
break;
case 0x3c: /* save */
save_state(dc, cpu_cond);