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https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
suspend: switch acpi s3 to new infrastructure.
This patch switches pc s3 suspend over to the new infrastructure. The cmos_s3 qemu_irq is killed, the new notifier is used instead. The xen hack goes away with that too, the hypercall can simply be done in a notifier function now. This patch also makes the guest actually stay suspended instead of leaving suspend instantly, so it is useful for more than just testing whenever the suspend/resume cycle actually works. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
parent
95b363b5c6
commit
da98c8eb4c
10 changed files with 47 additions and 42 deletions
32
hw/acpi.c
32
hw/acpi.c
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@ -248,6 +248,22 @@ int acpi_table_add(const char *t)
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}
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static void acpi_notify_wakeup(Notifier *notifier, void *data)
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{
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ACPIREGS *ar = container_of(notifier, ACPIREGS, wakeup);
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WakeupReason *reason = data;
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switch (*reason) {
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case QEMU_WAKEUP_REASON_OTHER:
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default:
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/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
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Pretend that resume was caused by power button */
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ar->pm1.evt.sts |=
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(ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
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break;
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}
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}
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/* ACPI PM1a EVT */
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uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar)
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{
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@ -333,9 +349,10 @@ void acpi_pm_tmr_reset(ACPIREGS *ar)
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}
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/* ACPI PM1aCNT */
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void acpi_pm1_cnt_init(ACPIREGS *ar, qemu_irq cmos_s3)
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void acpi_pm1_cnt_init(ACPIREGS *ar)
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{
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ar->pm1.cnt.cmos_s3 = cmos_s3;
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ar->wakeup.notify = acpi_notify_wakeup;
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qemu_register_wakeup_notifier(&ar->wakeup);
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}
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void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val)
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@ -350,12 +367,8 @@ void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val)
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qemu_system_shutdown_request();
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break;
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case 1:
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/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
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Pretend that resume was caused by power button */
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ar->pm1.evt.sts |=
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(ACPI_BITMASK_WAKE_STATUS | ACPI_BITMASK_POWER_BUTTON_STATUS);
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qemu_system_reset_request();
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qemu_irq_raise(ar->pm1.cnt.cmos_s3);
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qemu_system_suspend_request();
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break;
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default:
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break;
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}
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@ -376,9 +389,6 @@ void acpi_pm1_cnt_update(ACPIREGS *ar,
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void acpi_pm1_cnt_reset(ACPIREGS *ar)
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{
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ar->pm1.cnt.cnt = 0;
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if (ar->pm1.cnt.cmos_s3) {
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qemu_irq_lower(ar->pm1.cnt.cmos_s3);
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}
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}
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/* ACPI GPE */
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@ -96,7 +96,6 @@ struct ACPIPM1EVT {
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struct ACPIPM1CNT {
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uint16_t cnt;
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qemu_irq cmos_s3;
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};
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struct ACPIGPE {
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@ -114,6 +113,7 @@ struct ACPIREGS {
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ACPIPM1EVT evt;
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ACPIPM1CNT cnt;
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} pm1;
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Notifier wakeup;
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};
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/* PM_TMR */
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@ -138,7 +138,7 @@ void acpi_pm1_evt_power_down(ACPIREGS *ar);
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void acpi_pm1_evt_reset(ACPIREGS *ar);
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/* PM1a_CNT: piix and ich9 don't implement PM1b CNT. */
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void acpi_pm1_cnt_init(ACPIREGS *ar, qemu_irq cmos_s3);
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void acpi_pm1_cnt_init(ACPIREGS *ar);
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void acpi_pm1_cnt_write(ACPIREGS *ar, uint16_t val);
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void acpi_pm1_cnt_update(ACPIREGS *ar,
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bool sci_enable, bool sci_disable);
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@ -372,7 +372,7 @@ static int piix4_pm_initfn(PCIDevice *dev)
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}
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
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qemu_irq sci_irq, qemu_irq smi_irq,
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int kvm_enabled)
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{
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PCIDevice *dev;
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@ -383,7 +383,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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s = DO_UPCAST(PIIX4PMState, dev, dev);
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s->irq = sci_irq;
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acpi_pm1_cnt_init(&s->ar, cmos_s3);
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acpi_pm1_cnt_init(&s->ar);
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s->smi_irq = smi_irq;
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s->kvm_enabled = kvm_enabled;
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@ -102,6 +102,7 @@ typedef struct RTCState {
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QEMUTimer *second_timer2;
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Notifier clock_reset_notifier;
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LostTickPolicy lost_tick_policy;
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Notifier suspend_notifier;
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} RTCState;
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static void rtc_set_time(RTCState *s);
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@ -596,6 +597,14 @@ static void rtc_notify_clock_reset(Notifier *notifier, void *data)
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#endif
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}
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/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
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BIOS will read it and start S3 resume at POST Entry */
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static void rtc_notify_suspend(Notifier *notifier, void *data)
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{
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RTCState *s = container_of(notifier, RTCState, suspend_notifier);
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rtc_set_memory(&s->dev, 0xF, 0xFE);
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}
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static void rtc_reset(void *opaque)
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{
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RTCState *s = opaque;
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@ -676,6 +685,9 @@ static int rtc_initfn(ISADevice *dev)
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s->clock_reset_notifier.notify = rtc_notify_clock_reset;
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qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
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s->suspend_notifier.notify = rtc_notify_suspend;
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qemu_register_suspend_notifier(&s->suspend_notifier);
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s->next_second_time =
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qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
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qemu_mod_timer(s->second_timer2, s->next_second_time);
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@ -967,7 +967,7 @@ void mips_malta_init (ram_addr_t ram_size,
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pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
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usb_uhci_piix4_init(pci_bus, piix4_devfn + 2);
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smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
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isa_get_irq(NULL, 9), NULL, NULL, 0);
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isa_get_irq(NULL, 9), NULL, 0);
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/* TODO: Populate SPD eeprom data. */
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smbus_eeprom_init(smbus, 8, NULL, 0);
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pit = pit_init(isa_bus, 0x40, 0, NULL);
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11
hw/pc.c
11
hw/pc.c
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@ -914,17 +914,6 @@ static DeviceState *apic_init(void *env, uint8_t apic_id)
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return dev;
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}
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/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
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BIOS will read it and start S3 resume at POST Entry */
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void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
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{
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ISADevice *s = opaque;
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if (level) {
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rtc_set_memory(s, 0xF, 0xFE);
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}
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}
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void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
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{
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CPUState *s = opaque;
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3
hw/pc.h
3
hw/pc.h
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@ -103,7 +103,6 @@ void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
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extern int fd_bootchk;
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void pc_register_ferr_irq(qemu_irq irq);
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void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
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void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
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void pc_cpus_init(const char *cpu_model);
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@ -142,7 +141,7 @@ int acpi_table_add(const char *table_desc);
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/* acpi_piix.c */
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
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qemu_irq sci_irq, qemu_irq smi_irq,
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int kvm_enabled);
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void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
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@ -139,7 +139,6 @@ static void pc_init1(MemoryRegion *system_memory,
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qemu_irq *cpu_irq;
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qemu_irq *gsi;
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qemu_irq *i8259;
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qemu_irq *cmos_s3;
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qemu_irq *smi_irq;
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GSIState *gsi_state;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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@ -291,15 +290,10 @@ static void pc_init1(MemoryRegion *system_memory,
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if (pci_enabled && acpi_enabled) {
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i2c_bus *smbus;
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if (!xen_enabled()) {
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cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
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} else {
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cmos_s3 = qemu_allocate_irqs(xen_cmos_set_s3_resume, rtc_state, 1);
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}
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smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
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/* TODO: Populate SPD eeprom data. */
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smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
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gsi[9], *cmos_s3, *smi_irq,
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gsi[9], *smi_irq,
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kvm_enabled());
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smbus_eeprom_init(smbus, 8, NULL, 0);
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}
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@ -430,7 +430,7 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
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apm_init(&s->apm, NULL, s);
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acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
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acpi_pm1_cnt_init(&s->ar, NULL);
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acpi_pm1_cnt_init(&s->ar);
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pm_smbus_init(&s->dev.qdev, &s->smb);
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11
xen-all.c
11
xen-all.c
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@ -89,6 +89,7 @@ typedef struct XenIOState {
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const XenPhysmap *log_for_dirtybit;
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Notifier exit;
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Notifier suspend;
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} XenIOState;
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/* Xen specific function for piix pci */
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@ -121,12 +122,9 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
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}
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}
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void xen_cmos_set_s3_resume(void *opaque, int irq, int level)
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static void xen_suspend_notifier(Notifier *notifier, void *data)
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{
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pc_cmos_set_s3_resume(opaque, irq, level);
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if (level) {
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xc_set_hvm_param(xen_xc, xen_domid, HVM_PARAM_ACPI_S_STATE, 3);
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}
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xc_set_hvm_param(xen_xc, xen_domid, HVM_PARAM_ACPI_S_STATE, 3);
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}
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/* Xen Interrupt Controller */
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state->exit.notify = xen_exit_notifier;
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qemu_add_exit_notifier(&state->exit);
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state->suspend.notify = xen_suspend_notifier;
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qemu_register_suspend_notifier(&state->suspend);
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xc_get_hvm_param(xen_xc, xen_domid, HVM_PARAM_IOREQ_PFN, &ioreq_pfn);
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DPRINTF("shared page at pfn %lx\n", ioreq_pfn);
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state->shared_page = xc_map_foreign_range(xen_xc, xen_domid, XC_PAGE_SIZE,
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