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https://gitlab.com/qemu-project/qemu
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tcg-arm: Rearrange slow-path qemu_ld/st
Use the new helper_ret_*_mmu routines. Use a conditional call to arrange for a tail-call from the store path, and to load the return address for the helper for the load path. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
23bbc25085
commit
d9f4dde4a6
2 changed files with 87 additions and 104 deletions
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@ -324,21 +324,7 @@ extern uintptr_t tci_tb_ptr;
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In some implementations, we pass the "logical" return address manually;
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in others, we must infer the logical return from the true return. */
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#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
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# if defined(__arm__)
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/* We define two insns between the return address and the branch back to
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straight-line. Find and decode that branch insn. */
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# define GETRA_LDST(RA) tcg_getra_ldst(RA)
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static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
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{
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int32_t b;
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ra += 8; /* skip the two insns */
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b = *(int32_t *)ra; /* load the branch insn */
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b = (b << 8) >> (8 - 2); /* extract the displacement */
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ra += 8; /* branches are relative to pc+8 */
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ra += b; /* apply the displacement */
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return ra;
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}
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# elif defined(__aarch64__)
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# if defined(__aarch64__)
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# define GETRA_LDST(RA) tcg_getra_ldst(RA)
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static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
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{
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@ -175,11 +175,12 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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#ifdef CONFIG_SOFTMMU
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/* r0-r2 will be overwritten when reading the tlb entry,
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/* r0-r2,lr will be overwritten when reading the tlb entry,
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so don't use these. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
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#endif
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break;
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case 'L':
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@ -207,6 +208,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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/* Avoid clashes with registers being used for helper args */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
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#endif
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
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#endif
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break;
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@ -382,13 +384,17 @@ static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
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/* We pay attention here to not modify the branch target by skipping
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the corresponding bytes. This ensure that caches and memory are
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kept coherent during retranslation. */
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#ifdef HOST_WORDS_BIGENDIAN
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tcg_out8(s, (cond << 4) | 0x0a);
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s->code_ptr += 3;
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#else
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s->code_ptr += 3;
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tcg_out8(s, (cond << 4) | 0x0a);
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#endif
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}
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static inline void tcg_out_bl_noaddr(TCGContext *s, int cond)
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{
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/* We pay attention here to not modify the branch target by skipping
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the corresponding bytes. This ensure that caches and memory are
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kept coherent during retranslation. */
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s->code_ptr += 3;
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tcg_out8(s, (cond << 4) | 0x0b);
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}
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static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
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@ -1002,34 +1008,27 @@ static inline void tcg_out_st8(TCGContext *s, int cond,
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tcg_out_st8_12(s, cond, rd, rn, offset);
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}
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/* The _goto case is normally between TBs within the same code buffer,
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* and with the code buffer limited to 16MB we shouldn't need the long
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* case.
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*
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* .... except to the prologue that is in its own buffer.
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/* The _goto case is normally between TBs within the same code buffer, and
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* with the code buffer limited to 16MB we wouldn't need the long case.
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* But we also use it for the tail-call to the qemu_ld/st helpers, which does.
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*/
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static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
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{
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int32_t val;
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int32_t disp = addr - (tcg_target_long) s->code_ptr;
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if (addr & 1) {
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/* goto to a Thumb destination isn't supported */
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tcg_abort();
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if ((addr & 1) == 0 && disp - 8 < 0x01fffffd && disp - 8 > -0x01fffffd) {
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tcg_out_b(s, cond, disp);
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return;
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}
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val = addr - (tcg_target_long) s->code_ptr;
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if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
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tcg_out_b(s, cond, val);
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else {
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if (cond == COND_AL) {
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tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4);
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tcg_out32(s, addr);
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} else {
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tcg_out_movi32(s, cond, TCG_REG_TMP, val - 8);
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tcg_out_dat_reg(s, cond, ARITH_ADD,
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TCG_REG_PC, TCG_REG_PC,
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TCG_REG_TMP, SHIFT_IMM_LSL(0));
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tcg_out_movi32(s, cond, TCG_REG_TMP, addr);
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if (use_armv5t_instructions) {
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tcg_out_bx(s, cond, TCG_REG_TMP);
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} else {
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if (addr & 1) {
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tcg_abort();
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}
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tcg_out_mov_reg(s, cond, TCG_REG_PC, TCG_REG_TMP);
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}
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}
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@ -1084,23 +1083,29 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
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}
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#ifdef CONFIG_SOFTMMU
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* int mmu_idx, uintptr_t ra)
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*/
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static const void * const qemu_ld_helpers[8] = {
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helper_ret_ldub_mmu,
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helper_ret_lduw_mmu,
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helper_ret_ldul_mmu,
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helper_ret_ldq_mmu,
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/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
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int mmu_idx) */
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static const void * const qemu_ld_helpers[4] = {
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helper_ldb_mmu,
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helper_ldw_mmu,
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helper_ldl_mmu,
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helper_ldq_mmu,
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helper_ret_ldsb_mmu,
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helper_ret_ldsw_mmu,
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helper_ret_ldul_mmu,
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helper_ret_ldq_mmu,
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};
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/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
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uintxx_t val, int mmu_idx) */
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/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
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* uintxx_t val, int mmu_idx, uintptr_t ra)
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*/
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static const void * const qemu_st_helpers[4] = {
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helper_stb_mmu,
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helper_stw_mmu,
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helper_stl_mmu,
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helper_stq_mmu,
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helper_ret_stb_mmu,
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helper_ret_stw_mmu,
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helper_ret_stl_mmu,
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helper_ret_stq_mmu,
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};
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/* Helper routines for marshalling helper function arguments into
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@ -1259,7 +1264,8 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc,
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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TCGReg argreg, data_reg, data_reg2;
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uint8_t *start;
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int opc = lb->opc;
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uintptr_t func;
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reloc_pc24(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
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@ -1270,22 +1276,30 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
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}
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argreg = tcg_out_arg_imm32(s, argreg, lb->mem_index);
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tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[lb->opc & 3]);
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argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
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/* For armv6 we can use the canonical unsigned helpers and minimize
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icache usage. For pre-armv6, use the signed helpers since we do
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not have a single insn sign-extend. */
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if (use_armv6_instructions) {
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func = (uintptr_t)qemu_ld_helpers[opc & 3];
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} else {
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func = (uintptr_t)qemu_ld_helpers[opc];
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if (opc & 4) {
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opc = 2;
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}
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}
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tcg_out_call(s, func);
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data_reg = lb->datalo_reg;
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data_reg2 = lb->datahi_reg;
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start = s->code_ptr;
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switch (lb->opc) {
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switch (opc) {
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case 0 | 4:
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tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
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break;
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case 1 | 4:
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tcg_out_ext16s(s, COND_AL, data_reg, TCG_REG_R0);
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break;
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case 0:
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case 1:
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case 2:
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default:
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tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0);
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break;
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@ -1295,23 +1309,6 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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break;
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}
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/* For GETPC_LDST in exec-all.h, we architect exactly 2 insns between
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the call and the branch back to straight-line code. Note that the
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moves above could be elided by register allocation, nor do we know
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which code alternative we chose for extension. */
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switch (s->code_ptr - start) {
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case 0:
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tcg_out_nop(s);
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/* FALLTHRU */
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case 4:
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tcg_out_nop(s);
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/* FALLTHRU */
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case 8:
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break;
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default:
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abort();
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}
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tcg_out_goto(s, COND_AL, (tcg_target_long)lb->raddr);
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}
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@ -1347,13 +1344,10 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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}
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argreg = tcg_out_arg_imm32(s, argreg, lb->mem_index);
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tcg_out_call(s, (tcg_target_long) qemu_st_helpers[lb->opc & 3]);
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argreg = tcg_out_arg_reg32(s, argreg, TCG_REG_R14);
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/* For GETPC_LDST in exec-all.h, we architect exactly 2 insns between
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the call and the branch back to straight-line code. */
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tcg_out_nop(s);
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tcg_out_nop(s);
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tcg_out_goto(s, COND_AL, (tcg_target_long)lb->raddr);
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/* Tail-call to the helper, which will return to the fast path. */
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tcg_out_goto(s, COND_AL, (tcg_target_long) qemu_st_helpers[lb->opc & 3]);
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}
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#endif /* SOFTMMU */
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@ -1383,8 +1377,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read));
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/* This a conditional BL only to load a pointer within this opcode into LR
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for the slow path. We will not be using the value for a tail call. */
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label_ptr = s->code_ptr;
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tcg_out_b_noaddr(s, COND_NE);
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tcg_out_bl_noaddr(s, COND_NE);
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2,
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offsetof(CPUTLBEntry, addend)
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@ -1529,50 +1525,51 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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offsetof(CPUArchState,
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tlb_table[mem_index][0].addr_write));
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label_ptr = s->code_ptr;
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tcg_out_b_noaddr(s, COND_NE);
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_write));
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switch (opc) {
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case 0:
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tcg_out_st8_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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break;
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case 1:
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if (bswap) {
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tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, data_reg);
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tcg_out_st16_r(s, COND_AL, TCG_REG_R0, addr_reg, TCG_REG_R1);
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tcg_out_bswap16st(s, COND_EQ, TCG_REG_R0, data_reg);
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tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
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} else {
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tcg_out_st16_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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}
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break;
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case 2:
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default:
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if (bswap) {
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tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
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tcg_out_st32_r(s, COND_AL, TCG_REG_R0, addr_reg, TCG_REG_R1);
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tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
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tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
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} else {
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tcg_out_st32_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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}
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break;
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case 3:
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if (bswap) {
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tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
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tcg_out_st32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R1, addr_reg);
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tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
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tcg_out_st32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R1, 4);
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tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
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tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
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tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
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tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4);
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} else if (use_armv6_instructions
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&& (data_reg & 1) == 0 && data_reg2 == data_reg + 1) {
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tcg_out_strd_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_strd_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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} else {
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tcg_out_st32_rwb(s, COND_AL, data_reg, TCG_REG_R1, addr_reg);
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tcg_out_st32_12(s, COND_AL, data_reg2, TCG_REG_R1, 4);
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tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
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tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
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}
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break;
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}
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/* The conditional call must come last, as we're going to return here. */
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label_ptr = s->code_ptr;
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tcg_out_bl_noaddr(s, COND_NE);
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add_qemu_ldst_label(s, 0, opc, data_reg, data_reg2, addr_reg, addr_reg2,
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mem_index, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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