mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-10-15 15:32:51 +00:00
tcg/mips: move tcg_out_addsub2
Somehow the tcg_out_addsub2 function ended-up in the middle of the qemu_ld/st related functions. Move it with other arithmetics related functions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
parent
5eb4f645eb
commit
d9f26847f1
|
@ -567,6 +567,55 @@ static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
|
||||||
|
TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
|
||||||
|
bool cbh, bool is_sub)
|
||||||
|
{
|
||||||
|
TCGReg th = TCG_TMP1;
|
||||||
|
|
||||||
|
/* If we have a negative constant such that negating it would
|
||||||
|
make the high part zero, we can (usually) eliminate one insn. */
|
||||||
|
if (cbl && cbh && bh == -1 && bl != 0) {
|
||||||
|
bl = -bl;
|
||||||
|
bh = 0;
|
||||||
|
is_sub = !is_sub;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* By operating on the high part first, we get to use the final
|
||||||
|
carry operation to move back from the temporary. */
|
||||||
|
if (!cbh) {
|
||||||
|
tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
|
||||||
|
} else if (bh != 0 || ah == rl) {
|
||||||
|
tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
|
||||||
|
} else {
|
||||||
|
th = ah;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Note that tcg optimization should eliminate the bl == 0 case. */
|
||||||
|
if (is_sub) {
|
||||||
|
if (cbl) {
|
||||||
|
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
|
||||||
|
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
|
||||||
|
} else {
|
||||||
|
tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
|
||||||
|
tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
|
||||||
|
}
|
||||||
|
tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
|
||||||
|
} else {
|
||||||
|
if (cbl) {
|
||||||
|
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
|
||||||
|
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
|
||||||
|
} else if (rl == al && rl == bl) {
|
||||||
|
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, 31);
|
||||||
|
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
|
||||||
|
} else {
|
||||||
|
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
|
||||||
|
tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
|
||||||
|
}
|
||||||
|
tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/* Bit 0 set if inversion required; bit 1 set if swapping required. */
|
/* Bit 0 set if inversion required; bit 1 set if swapping required. */
|
||||||
#define MIPS_CMP_INV 1
|
#define MIPS_CMP_INV 1
|
||||||
#define MIPS_CMP_SWAP 2
|
#define MIPS_CMP_SWAP 2
|
||||||
|
@ -1237,55 +1286,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
|
|
||||||
TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
|
|
||||||
bool cbh, bool is_sub)
|
|
||||||
{
|
|
||||||
TCGReg th = TCG_TMP1;
|
|
||||||
|
|
||||||
/* If we have a negative constant such that negating it would
|
|
||||||
make the high part zero, we can (usually) eliminate one insn. */
|
|
||||||
if (cbl && cbh && bh == -1 && bl != 0) {
|
|
||||||
bl = -bl;
|
|
||||||
bh = 0;
|
|
||||||
is_sub = !is_sub;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* By operating on the high part first, we get to use the final
|
|
||||||
carry operation to move back from the temporary. */
|
|
||||||
if (!cbh) {
|
|
||||||
tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
|
|
||||||
} else if (bh != 0 || ah == rl) {
|
|
||||||
tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
|
|
||||||
} else {
|
|
||||||
th = ah;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Note that tcg optimization should eliminate the bl == 0 case. */
|
|
||||||
if (is_sub) {
|
|
||||||
if (cbl) {
|
|
||||||
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
|
|
||||||
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
|
|
||||||
} else {
|
|
||||||
tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
|
|
||||||
tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
|
|
||||||
}
|
|
||||||
tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
|
|
||||||
} else {
|
|
||||||
if (cbl) {
|
|
||||||
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
|
|
||||||
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
|
|
||||||
} else if (rl == al && rl == bl) {
|
|
||||||
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, 31);
|
|
||||||
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
|
|
||||||
} else {
|
|
||||||
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
|
|
||||||
tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
|
|
||||||
}
|
|
||||||
tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
|
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
|
||||||
{
|
{
|
||||||
TCGReg addr_regl, addr_regh __attribute__((unused));
|
TCGReg addr_regl, addr_regh __attribute__((unused));
|
||||||
|
|
Loading…
Reference in a new issue