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target/microblaze: Ensure imm constant is always available
Include the env->imm value in the TB values when IMM_FLAG is set. This means that we can always reconstruct the complete 32-bit imm. Discard env_imm when its contents can no longer be accessed. Fix user-mode checks for BRK/BRKI, which depend on IMM. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -374,9 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->pc;
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*cs_base = 0;
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*flags = (env->iflags & IFLAGS_TB_MASK) |
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(env->msr & (MSR_UM | MSR_VM | MSR_EE));
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*cs_base = (*flags & IMM_FLAG ? env->imm : 0);
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}
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#if !defined(CONFIG_USER_ONLY)
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@ -61,6 +61,7 @@ typedef struct DisasContext {
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/* Decoder. */
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int type_b;
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uint32_t ir;
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uint32_t ext_imm;
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uint8_t opcode;
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uint8_t rd, ra, rb;
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uint16_t imm;
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@ -169,24 +170,23 @@ static bool trap_userspace(DisasContext *dc, bool cond)
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return cond_user;
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}
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/* True if ALU operand b is a small immediate that may deserve
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faster treatment. */
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static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
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static int32_t dec_alu_typeb_imm(DisasContext *dc)
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{
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/* Immediate insn without the imm prefix ? */
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return dc->type_b && !(dc->tb_flags & IMM_FLAG);
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tcg_debug_assert(dc->type_b);
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if (dc->tb_flags & IMM_FLAG) {
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return dc->ext_imm | dc->imm;
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} else {
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return (int16_t)dc->imm;
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}
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}
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static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc)
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{
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if (dc->type_b) {
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if (dc->tb_flags & IMM_FLAG)
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tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm);
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else
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tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm));
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tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc));
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return &cpu_imm;
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} else
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return &cpu_R[dc->rb];
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}
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return &cpu_R[dc->rb];
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}
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static void dec_add(DisasContext *dc)
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@ -776,14 +776,14 @@ static inline void sync_jmpstate(DisasContext *dc)
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static void dec_imm(DisasContext *dc)
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{
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tcg_gen_movi_i32(cpu_imm, (dc->imm << 16));
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dc->ext_imm = dc->imm << 16;
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tcg_gen_movi_i32(cpu_imm, dc->ext_imm);
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dc->tb_flags |= IMM_FLAG;
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dc->clear_imm = 0;
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}
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static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t)
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{
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bool extimm = dc->tb_flags & IMM_FLAG;
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/* Should be set to true if r1 is used by loadstores. */
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bool stackprot = false;
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TCGv_i32 t32;
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@ -836,11 +836,7 @@ static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t)
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}
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/* Immediate. */
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t32 = tcg_temp_new_i32();
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if (!extimm) {
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tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm);
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} else {
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tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
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}
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tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc));
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tcg_gen_extu_i32_tl(t, t32);
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tcg_temp_free_i32(t32);
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@ -1134,15 +1130,13 @@ static void dec_bcc(DisasContext *dc)
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dec_setup_dslot(dc);
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}
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if (dec_alu_op_b_is_small_imm(dc)) {
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int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
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tcg_gen_movi_i32(cpu_btarget, dc->base.pc_next + offset);
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if (dc->type_b) {
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dc->jmp = JMP_DIRECT_CC;
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dc->jmp_pc = dc->base.pc_next + offset;
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dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc);
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tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc);
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} else {
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dc->jmp = JMP_INDIRECT;
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next);
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tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next);
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}
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eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]);
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}
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@ -1192,38 +1186,63 @@ static void dec_br(DisasContext *dc)
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return;
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}
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if (abs && link && !dslot) {
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if (dc->type_b) {
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/* BRKI */
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uint32_t imm = dec_alu_typeb_imm(dc);
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if (trap_userspace(dc, imm != 8 && imm != 0x18)) {
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return;
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}
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} else {
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/* BRK */
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if (trap_userspace(dc, true)) {
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return;
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}
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}
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}
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dc->delayed_branch = 1;
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if (dslot) {
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dec_setup_dslot(dc);
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}
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if (link && dc->rd)
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if (link && dc->rd) {
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tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next);
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}
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dc->jmp = JMP_INDIRECT;
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if (abs) {
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tcg_gen_movi_i32(cpu_btaken, 1);
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tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc)));
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if (link && !dslot) {
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if (!(dc->tb_flags & IMM_FLAG) &&
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(dc->imm == 8 || dc->imm == 0x18)) {
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if (dc->type_b) {
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uint32_t dest = dec_alu_typeb_imm(dc);
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dc->jmp = JMP_DIRECT;
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dc->jmp_pc = dest;
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tcg_gen_movi_i32(cpu_btarget, dest);
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if (link && !dslot) {
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switch (dest) {
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case 8:
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case 0x18:
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gen_raise_exception_sync(dc, EXCP_BREAK);
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break;
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case 0:
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gen_raise_exception_sync(dc, EXCP_DEBUG);
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break;
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}
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}
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} else {
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dc->jmp = JMP_INDIRECT;
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tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]);
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if (link && !dslot) {
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gen_raise_exception_sync(dc, EXCP_BREAK);
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}
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if (dc->imm == 0) {
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if (trap_userspace(dc, true)) {
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return;
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}
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gen_raise_exception_sync(dc, EXCP_DEBUG);
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}
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}
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} else if (dc->type_b) {
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dc->jmp = JMP_DIRECT;
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dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc);
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tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc);
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} else {
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if (dec_alu_op_b_is_small_imm(dc)) {
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dc->jmp = JMP_DIRECT;
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dc->jmp_pc = dc->base.pc_next + (int32_t)((int16_t)dc->imm);
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} else {
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tcg_gen_movi_i32(cpu_btaken, 1);
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tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->base.pc_next);
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}
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dc->jmp = JMP_INDIRECT;
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tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next);
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}
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tcg_gen_movi_i32(cpu_btaken, 1);
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}
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static inline void do_rti(DisasContext *dc)
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@ -1529,6 +1548,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP;
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dc->cpustate_changed = 0;
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dc->abort_at_next_insn = 0;
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dc->ext_imm = dc->base.tb->cs_base;
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bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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dc->base.max_insns = MIN(dc->base.max_insns, bound);
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@ -1573,8 +1593,9 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
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dc->clear_imm = 1;
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decode(dc, cpu_ldl_code(env, dc->base.pc_next));
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if (dc->clear_imm) {
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if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) {
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dc->tb_flags &= ~IMM_FLAG;
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tcg_gen_discard_i32(cpu_imm);
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}
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dc->base.pc_next += 4;
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