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x86: cpu: fixup number of addressable IDs for logical processors sharing cache
When QEMU is started with '-cpu host,host-cache-info=on', it will passthrough host's number of logical processors sharing cache and number of processor cores in the physical package. QEMU already fixes up the later to correctly reflect number of configured cores for VM, however number of logical processors sharing cache is still comes from host CPU, which confuses guest started with: -machine q35,accel=kvm \ -cpu host,host-cache-info=on,l3-cache=off \ -smp 20,sockets=2,dies=1,cores=10,threads=1 \ -numa node,nodeid=0,memdev=ram-node0 \ -numa node,nodeid=1,memdev=ram-node1 \ -numa cpu,socket-id=0,node-id=0 \ -numa cpu,socket-id=1,node-id=1 on 2 socket Xeon 4210R host with 10 cores per socket with CPUID[04H]: ... --- cache 3 --- cache type = unified cache (3) cache level = 0x3 (3) self-initializing cache level = true fully associative cache = false maximum IDs for CPUs sharing cache = 0x1f (31) maximum IDs for cores in pkg = 0xf (15) ... that doesn't match number of logical processors VM was configured with and as result RHEL 9.0 guest complains: sched: CPU #10's llc-sibling CPU #0 is not on the same node! [node: 1 != 0]. Ignoring dependency. WARNING: CPU: 10 PID: 0 at arch/x86/kernel/smpboot.c:421 topology_sane.isra.0+0x67/0x80 ... Call Trace: set_cpu_sibling_map+0x176/0x590 start_secondary+0x5b/0x150 secondary_startup_64_no_verify+0xc2/0xcb Fix it by capping max number of logical processors to vcpus/socket as it was configured, which fixes the issue. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2088311 Message-Id: <20220524151020.2541698-3-imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -5284,10 +5284,22 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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/* cache info: needed for Core compatibility */
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if (cpu->cache_info_passthrough) {
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x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx);
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/* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
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*eax &= ~0xFC000000;
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if ((*eax & 31) && cs->nr_cores > 1) {
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*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
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/*
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* QEMU has its own number of cores/logical cpus,
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* set 24..14, 31..26 bit to configured values
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*/
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if (*eax & 31) {
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int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14);
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int vcpus_per_socket = env->nr_dies * cs->nr_cores *
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cs->nr_threads;
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if (cs->nr_cores > 1) {
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*eax &= ~0xFC000000;
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*eax |= (pow2ceil(cs->nr_cores) - 1) << 26;
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}
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if (host_vcpus_per_cache > vcpus_per_socket) {
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*eax &= ~0x3FFC000;
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*eax |= (pow2ceil(vcpus_per_socket) - 1) << 14;
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}
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}
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} else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
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*eax = *ebx = *ecx = *edx = 0;
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