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x86_64 support

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1320 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2005-03-01 22:33:42 +00:00
parent 5e83e8e3e7
commit d785e6be4d
3 changed files with 55 additions and 57 deletions
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1
dyngen-exec.h
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@ -221,6 +221,7 @@ extern int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
#endif
#ifdef __x86_64__
#define EXIT_TB() asm volatile ("ret")
#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n)
#endif
#ifdef __powerpc__
#define EXIT_TB() asm volatile ("blr")

107
target-i386/exec.h
View file

@ -21,78 +21,75 @@
#include "dyngen-exec.h"
/* XXX: factorize this mess */
#if defined(__alpha__) || defined (__ia64__) || defined(__x86_64__)
#define HOST_LONG_BITS 64
#else
#define HOST_LONG_BITS 32
#endif
#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
#endif
#include "cpu-defs.h"
/* at least 4 register variables are defined */
register struct CPUX86State *env asm(AREG0);
/* XXX: use 64 bit regs if HOST_LONG_BITS == 64 */
#if TARGET_LONG_BITS == 32
register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
register uint32_t T2 asm(AREG3);
/* if more registers are available, we define some registers too */
#ifdef AREG4
register uint32_t EAX asm(AREG4);
#define reg_EAX
#endif
#ifdef AREG5
register uint32_t ESP asm(AREG5);
#define reg_ESP
#endif
#ifdef AREG6
register uint32_t EBP asm(AREG6);
#define reg_EBP
#endif
#ifdef AREG7
register uint32_t ECX asm(AREG7);
#define reg_ECX
#endif
#ifdef AREG8
register uint32_t EDX asm(AREG8);
#define reg_EDX
#endif
#ifdef AREG9
register uint32_t EBX asm(AREG9);
#define reg_EBX
#endif
#ifdef AREG10
register uint32_t ESI asm(AREG10);
#define reg_ESI
#endif
#ifdef AREG11
register uint32_t EDI asm(AREG11);
#define reg_EDI
#endif
#else
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* no registers can be used */
#define T0 (env->t0)
#define T1 (env->t1)
#define T2 (env->t2)
#else
/* XXX: use unsigned long instead of target_ulong - better code will
be generated for 64 bit CPUs */
register target_ulong T0 asm(AREG1);
register target_ulong T1 asm(AREG2);
register target_ulong T2 asm(AREG3);
/* if more registers are available, we define some registers too */
#ifdef AREG4
register target_ulong EAX asm(AREG4);
#define reg_EAX
#endif
#ifdef AREG5
register target_ulong ESP asm(AREG5);
#define reg_ESP
#endif
#ifdef AREG6
register target_ulong EBP asm(AREG6);
#define reg_EBP
#endif
#ifdef AREG7
register target_ulong ECX asm(AREG7);
#define reg_ECX
#endif
#ifdef AREG8
register target_ulong EDX asm(AREG8);
#define reg_EDX
#endif
#ifdef AREG9
register target_ulong EBX asm(AREG9);
#define reg_EBX
#endif
#ifdef AREG10
register target_ulong ESI asm(AREG10);
#define reg_ESI
#endif
#ifdef AREG11
register target_ulong EDI asm(AREG11);
#define reg_EDI
#endif
#endif /* ! (TARGET_LONG_BITS > HOST_LONG_BITS) */
#define A0 T2
extern FILE *logfile;

4
target-sparc/translate.c
View file

@ -1690,7 +1690,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
}
#if defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr;
}
@ -1700,7 +1700,7 @@ extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, in
int *access_index, target_ulong address, int rw,
int is_user);
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
target_phys_addr_t phys_addr;
int prot, access_index;