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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 01:43:39 +00:00
Hexagon (target/hexagon) implement mutability mask for GPRs
Some registers are defined to have immutable bits, this commit will implement that behavior. Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com>
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@ -43,6 +43,33 @@ TCGv gen_read_preg(TCGv pred, uint8_t num)
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return pred;
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}
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#define IMMUTABLE (~0)
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static const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS] = {
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[HEX_REG_USR] = 0xc13000c0,
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[HEX_REG_PC] = IMMUTABLE,
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[HEX_REG_GP] = 0x3f,
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[HEX_REG_UPCYCLELO] = IMMUTABLE,
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[HEX_REG_UPCYCLEHI] = IMMUTABLE,
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[HEX_REG_UTIMERLO] = IMMUTABLE,
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[HEX_REG_UTIMERHI] = IMMUTABLE,
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};
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static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val,
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target_ulong reg_mask)
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{
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if (reg_mask) {
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TCGv tmp = tcg_temp_new();
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/* new_val = (new_val & ~reg_mask) | (cur_val & reg_mask) */
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tcg_gen_andi_tl(new_val, new_val, ~reg_mask);
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tcg_gen_andi_tl(tmp, cur_val, reg_mask);
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tcg_gen_or_tl(new_val, new_val, tmp);
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tcg_temp_free(tmp);
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}
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}
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static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
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uint32_t slot)
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{
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@ -69,6 +96,9 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
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void gen_log_reg_write(int rnum, TCGv val)
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{
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const target_ulong reg_mask = reg_immut_masks[rnum];
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gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
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tcg_gen_mov_tl(hex_new_value[rnum], val);
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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@ -114,19 +144,29 @@ static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
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static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
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{
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const target_ulong reg_mask_low = reg_immut_masks[rnum];
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const target_ulong reg_mask_high = reg_immut_masks[rnum + 1];
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TCGv val32 = tcg_temp_new();
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/* Low word */
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tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
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tcg_gen_extrl_i64_i32(val32, val);
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gen_masked_reg_write(val32, hex_gpr[rnum], reg_mask_low);
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tcg_gen_mov_tl(hex_new_value[rnum], val32);
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum], 1);
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}
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/* High word */
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tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
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tcg_gen_extrh_i64_i32(val32, val);
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gen_masked_reg_write(val32, hex_gpr[rnum + 1], reg_mask_high);
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tcg_gen_mov_tl(hex_new_value[rnum + 1], val32);
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
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}
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tcg_temp_free(val32);
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}
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void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
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@ -44,6 +44,7 @@ HEX_TESTS += atomics
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HEX_TESTS += fpstuff
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HEX_TESTS += overflow
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HEX_TESTS += signal_context
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HEX_TESTS += reg_mut
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HEX_TESTS += test_abs
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HEX_TESTS += test_bitcnt
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152
tests/tcg/hexagon/reg_mut.c
Normal file
152
tests/tcg/hexagon/reg_mut.c
Normal file
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@ -0,0 +1,152 @@
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/*
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* Copyright(c) 2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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#include <stdint.h>
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static int err;
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#define check(N, EXPECT) \
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do { \
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uint64_t value = N; \
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uint64_t expect = EXPECT; \
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if (value != EXPECT) { \
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printf("ERROR: \"%s\" 0x%04llx != 0x%04llx at %s:%d\n", #N, value, \
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expect, __FILE__, __LINE__); \
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err++; \
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} \
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} while (0)
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#define check_ne(N, EXPECT) \
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do { \
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uint64_t value = N; \
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uint64_t expect = EXPECT; \
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if (value == EXPECT) { \
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printf("ERROR: \"%s\" 0x%04llx == 0x%04llx at %s:%d\n", #N, value, \
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expect, __FILE__, __LINE__); \
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err++; \
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} \
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} while (0)
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#define WRITE_REG_NOCLOBBER(output, reg_name, input) \
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asm volatile(reg_name " = %1\n\t" \
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"%0 = " reg_name "\n\t" \
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: "=r"(output) \
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: "r"(input) \
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: );
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#define WRITE_REG_ENCODED(output, reg_name, input, encoding) \
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asm volatile("r0 = %1\n\t" \
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encoding "\n\t" \
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"%0 = " reg_name "\n\t" \
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: "=r"(output) \
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: "r"(input) \
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: "r0");
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#define WRITE_REG_PAIR_ENCODED(output, reg_name, input, encoding) \
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asm volatile("r1:0 = %1\n\t" \
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encoding "\n\t" \
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"%0 = " reg_name "\n\t" \
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: "=r"(output) \
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: "r"(input) \
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: "r1:0");
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/*
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* Instruction word: { pc = r0 }
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*
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* This instruction is barred by the assembler.
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | Opc[A2_tfrrcr] | Src[R0] |P P| | C9/PC |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*/
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#define PC_EQ_R0 ".word 0x6220c009"
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#define C9_8_EQ_R1_0 ".word 0x6320c008"
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static inline void write_control_registers(void)
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{
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uint32_t result = 0;
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WRITE_REG_NOCLOBBER(result, "usr", 0xffffffff);
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check(result, 0x3ecfff3f);
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WRITE_REG_NOCLOBBER(result, "gp", 0xffffffff);
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check(result, 0xffffffc0);
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WRITE_REG_NOCLOBBER(result, "upcyclelo", 0xffffffff);
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check(result, 0x00000000);
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WRITE_REG_NOCLOBBER(result, "upcyclehi", 0xffffffff);
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check(result, 0x00000000);
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WRITE_REG_NOCLOBBER(result, "utimerlo", 0xffffffff);
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check(result, 0x00000000);
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WRITE_REG_NOCLOBBER(result, "utimerhi", 0xffffffff);
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check(result, 0x00000000);
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/*
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* PC is special. Setting it to these values
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* should cause a catastrophic failure.
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*/
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WRITE_REG_ENCODED(result, "pc", 0x00000000, PC_EQ_R0);
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check_ne(result, 0x00000000);
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WRITE_REG_ENCODED(result, "pc", 0x00000001, PC_EQ_R0);
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check_ne(result, 0x00000001);
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WRITE_REG_ENCODED(result, "pc", 0xffffffff, PC_EQ_R0);
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check_ne(result, 0xffffffff);
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}
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static inline void write_control_register_pairs(void)
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{
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uint64_t result = 0;
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WRITE_REG_NOCLOBBER(result, "c11:10", 0xffffffffffffffff);
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check(result, 0xffffffc0ffffffff);
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WRITE_REG_NOCLOBBER(result, "c15:14", 0xffffffffffffffff);
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check(result, 0x0000000000000000);
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WRITE_REG_NOCLOBBER(result, "c31:30", 0xffffffffffffffff);
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check(result, 0x0000000000000000);
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WRITE_REG_PAIR_ENCODED(result, "c9:8", (uint64_t) 0x0000000000000000,
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C9_8_EQ_R1_0);
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check_ne(result, 0x000000000000000);
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WRITE_REG_PAIR_ENCODED(result, "c9:8", 0x0000000100000000, C9_8_EQ_R1_0);
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check_ne(result, 0x0000000100000000);
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WRITE_REG_PAIR_ENCODED(result, "c9:8", 0xffffffffffffffff, C9_8_EQ_R1_0);
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check_ne(result, 0xffffffffffffffff);
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}
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int main()
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{
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err = 0;
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write_control_registers();
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write_control_register_pairs();
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puts(err ? "FAIL" : "PASS");
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return err;
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}
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