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target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h
We will need these functions in translate-sme.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -107,6 +107,44 @@ static inline int vec_full_reg_size(DisasContext *s)
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return s->vl;
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}
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/*
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* Return the offset info CPUARMState of the predicate vector register Pn.
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* Note for this purpose, FFR is P16.
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*/
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static inline int pred_full_reg_offset(DisasContext *s, int regno)
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{
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return offsetof(CPUARMState, vfp.pregs[regno]);
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}
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/* Return the byte size of the whole predicate register, VL / 64. */
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static inline int pred_full_reg_size(DisasContext *s)
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{
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return s->vl >> 3;
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}
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/*
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* Round up the size of a register to a size allowed by
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* the tcg vector infrastructure. Any operation which uses this
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* size may assume that the bits above pred_full_reg_size are zero,
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* and must leave them the same way.
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*
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* Note that this is not needed for the vector registers as they
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* are always properly sized for tcg vectors.
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*/
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static inline int size_for_gvec(int size)
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{
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if (size <= 8) {
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return 8;
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} else {
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return QEMU_ALIGN_UP(size, 16);
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}
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}
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static inline int pred_gvec_reg_size(DisasContext *s)
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{
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return size_for_gvec(pred_full_reg_size(s));
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}
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bool disas_sve(DisasContext *, uint32_t);
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void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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@ -100,42 +100,6 @@ static inline int msz_dtype(DisasContext *s, int msz)
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* Implement all of the translator functions referenced by the decoder.
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*/
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/* Return the offset info CPUARMState of the predicate vector register Pn.
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* Note for this purpose, FFR is P16.
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*/
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static inline int pred_full_reg_offset(DisasContext *s, int regno)
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{
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return offsetof(CPUARMState, vfp.pregs[regno]);
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}
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/* Return the byte size of the whole predicate register, VL / 64. */
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static inline int pred_full_reg_size(DisasContext *s)
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{
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return s->vl >> 3;
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}
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/* Round up the size of a register to a size allowed by
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* the tcg vector infrastructure. Any operation which uses this
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* size may assume that the bits above pred_full_reg_size are zero,
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* and must leave them the same way.
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*
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* Note that this is not needed for the vector registers as they
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* are always properly sized for tcg vectors.
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*/
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static int size_for_gvec(int size)
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{
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if (size <= 8) {
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return 8;
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} else {
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return QEMU_ALIGN_UP(size, 16);
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}
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}
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static int pred_gvec_reg_size(DisasContext *s)
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{
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return size_for_gvec(pred_full_reg_size(s));
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}
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/* Invoke an out-of-line helper on 2 Zregs. */
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static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
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int rd, int rn, int data)
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