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https://gitlab.com/qemu-project/qemu
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use constant IOPORTS_MASK instead of 0xffff.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
parent
3299397760
commit
d56dd6cf03
5 changed files with 16 additions and 15 deletions
12
hw/apb_pci.c
12
hw/apb_pci.c
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@ -148,26 +148,26 @@ static CPUReadMemoryFunc *pci_apb_read[] = {
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outb(NULL, addr & 0xffff, val);
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cpu_outb(NULL, addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outw(NULL, addr & 0xffff, val);
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cpu_outw(NULL, addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outl(NULL, addr & 0xffff, val);
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cpu_outl(NULL, addr & IOPORTS_MASK, val);
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}
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inb(NULL, addr & 0xffff);
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val = cpu_inb(NULL, addr & IOPORTS_MASK);
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return val;
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}
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@ -175,7 +175,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inw(NULL, addr & 0xffff);
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val = cpu_inw(NULL, addr & IOPORTS_MASK);
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return val;
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}
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@ -183,7 +183,7 @@ static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inl(NULL, addr & 0xffff);
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val = cpu_inl(NULL, addr & IOPORTS_MASK);
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return val;
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}
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@ -28,7 +28,7 @@
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static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outb(NULL, addr & 0xffff, val);
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cpu_outb(NULL, addr & IOPORTS_MASK, val);
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}
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static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
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@ -37,7 +37,7 @@ static void isa_mmio_writew (void *opaque, target_phys_addr_t addr,
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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cpu_outw(NULL, addr & 0xffff, val);
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cpu_outw(NULL, addr & IOPORTS_MASK, val);
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}
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static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
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@ -46,14 +46,14 @@ static void isa_mmio_writel (void *opaque, target_phys_addr_t addr,
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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cpu_outl(NULL, addr & 0xffff, val);
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cpu_outl(NULL, addr & IOPORTS_MASK, val);
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}
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static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inb(NULL, addr & 0xffff);
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val = cpu_inb(NULL, addr & IOPORTS_MASK);
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return val;
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}
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@ -61,7 +61,7 @@ static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inw(NULL, addr & 0xffff);
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val = cpu_inw(NULL, addr & IOPORTS_MASK);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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@ -72,7 +72,7 @@ static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inl(NULL, addr & 0xffff);
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val = cpu_inl(NULL, addr & IOPORTS_MASK);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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4
ioport.c
4
ioport.c
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@ -94,7 +94,7 @@ static uint32_t default_ioport_readw(void *opaque, uint32_t address)
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{
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uint32_t data;
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data = ioport_read(0, address);
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address = (address + 1) & (MAX_IOPORTS - 1);
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address = (address + 1) & IOPORTS_MASK;
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data |= ioport_read(0, address) << 8;
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return data;
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}
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@ -102,7 +102,7 @@ static uint32_t default_ioport_readw(void *opaque, uint32_t address)
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static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
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{
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ioport_write(0, address, data & 0xff);
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address = (address + 1) & (MAX_IOPORTS - 1);
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address = (address + 1) & IOPORTS_MASK;
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ioport_write(0, address, (data >> 8) & 0xff);
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}
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1
ioport.h
1
ioport.h
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@ -28,6 +28,7 @@
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#include "qemu-common.h"
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#define MAX_IOPORTS (64 * 1024)
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#define IOPORTS_MASK (MAX_IOPORTS - 1)
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/* These should really be in isa.h, but are here to make pc.h happy. */
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typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
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@ -1161,7 +1161,7 @@ static void do_ioport_read(Monitor *mon, int count, int format, int size,
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int suffix;
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if (has_index) {
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cpu_outb(NULL, addr & 0xffff, index & 0xff);
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cpu_outb(NULL, addr & IOPORTS_MASK, index & 0xff);
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addr++;
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}
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addr &= 0xffff;
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