mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
target-arm: Fix errors in decode of M profile CPS
Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17 This fixes an issue reported as LP:913925. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
6b620ca3b0
commit
d3cb6e2b06
1 changed files with 4 additions and 4 deletions
|
@ -9710,15 +9710,15 @@ static void disas_thumb_insn(CPUState *env, DisasContext *s)
|
|||
break;
|
||||
if (IS_M(env)) {
|
||||
tmp = tcg_const_i32((insn & (1 << 4)) != 0);
|
||||
/* PRIMASK */
|
||||
/* FAULTMASK */
|
||||
if (insn & 1) {
|
||||
addr = tcg_const_i32(16);
|
||||
addr = tcg_const_i32(19);
|
||||
gen_helper_v7m_msr(cpu_env, addr, tmp);
|
||||
tcg_temp_free_i32(addr);
|
||||
}
|
||||
/* FAULTMASK */
|
||||
/* PRIMASK */
|
||||
if (insn & 2) {
|
||||
addr = tcg_const_i32(17);
|
||||
addr = tcg_const_i32(16);
|
||||
gen_helper_v7m_msr(cpu_env, addr, tmp);
|
||||
tcg_temp_free_i32(addr);
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue