mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
target/arm: Avoid bare abort() or assert(0)
Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
87c3f0f2f7
commit
d385a60571
8 changed files with 15 additions and 16 deletions
|
@ -8740,8 +8740,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
/* broken reginfo with out-of-range opc1 */
|
/* broken reginfo with out-of-range opc1 */
|
||||||
assert(false);
|
g_assert_not_reached();
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
/* assert our permissions are not too lax (stricter is fine) */
|
/* assert our permissions are not too lax (stricter is fine) */
|
||||||
assert((r->access & ~mask) == 0);
|
assert((r->access & ~mask) == 0);
|
||||||
|
@ -10823,7 +10822,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
/* Never happens, but compiler isn't smart enough to tell. */
|
/* Never happens, but compiler isn't smart enough to tell. */
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
|
*prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
|
||||||
|
@ -10944,7 +10943,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
/* Never happens, but compiler isn't smart enough to tell. */
|
/* Never happens, but compiler isn't smart enough to tell. */
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (domain_prot == 3) {
|
if (domain_prot == 3) {
|
||||||
|
|
|
@ -1200,7 +1200,7 @@ int hvf_vcpu_exec(CPUState *cpu)
|
||||||
/* we got kicked, no exit to process */
|
/* we got kicked, no exit to process */
|
||||||
return 0;
|
return 0;
|
||||||
default:
|
default:
|
||||||
assert(0);
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
|
|
||||||
hvf_sync_vtimer(cpu);
|
hvf_sync_vtimer(cpu);
|
||||||
|
|
|
@ -15,10 +15,10 @@
|
||||||
|
|
||||||
bool write_kvmstate_to_list(ARMCPU *cpu)
|
bool write_kvmstate_to_list(ARMCPU *cpu)
|
||||||
{
|
{
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
|
|
||||||
bool write_list_to_kvmstate(ARMCPU *cpu, int level)
|
bool write_list_to_kvmstate(ARMCPU *cpu, int level)
|
||||||
{
|
{
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
|
|
|
@ -540,7 +540,7 @@ bool write_kvmstate_to_list(ARMCPU *cpu)
|
||||||
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
if (ret) {
|
if (ret) {
|
||||||
ok = false;
|
ok = false;
|
||||||
|
@ -575,7 +575,7 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
|
||||||
r.addr = (uintptr_t)(cpu->cpreg_values + i);
|
r.addr = (uintptr_t)(cpu->cpreg_values + i);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
|
|
|
@ -661,7 +661,7 @@ static int cpu_pre_save(void *opaque)
|
||||||
if (kvm_enabled()) {
|
if (kvm_enabled()) {
|
||||||
if (!write_kvmstate_to_list(cpu)) {
|
if (!write_kvmstate_to_list(cpu)) {
|
||||||
/* This should never fail */
|
/* This should never fail */
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -672,7 +672,7 @@ static int cpu_pre_save(void *opaque)
|
||||||
} else {
|
} else {
|
||||||
if (!write_cpustate_to_list(cpu, false)) {
|
if (!write_cpustate_to_list(cpu, false)) {
|
||||||
/* This should never fail. */
|
/* This should never fail. */
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -6151,7 +6151,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
|
||||||
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
|
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
|
|
||||||
write_fp_sreg(s, rd, tcg_res);
|
write_fp_sreg(s, rd, tcg_res);
|
||||||
|
@ -6392,7 +6392,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
default:
|
default:
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -679,7 +679,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
if ((vd + a->stride * (nregs - 1)) > 31) {
|
if ((vd + a->stride * (nregs - 1)) > 31) {
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -5156,7 +5156,7 @@ static void gen_srs(DisasContext *s,
|
||||||
offset = 4;
|
offset = 4;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
tcg_gen_addi_i32(addr, addr, offset);
|
tcg_gen_addi_i32(addr, addr, offset);
|
||||||
tmp = load_reg(s, 14);
|
tmp = load_reg(s, 14);
|
||||||
|
@ -5181,7 +5181,7 @@ static void gen_srs(DisasContext *s,
|
||||||
offset = 0;
|
offset = 0;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
abort();
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
tcg_gen_addi_i32(addr, addr, offset);
|
tcg_gen_addi_i32(addr, addr, offset);
|
||||||
gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
|
gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
|
||||||
|
|
Loading…
Reference in a new issue