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https://gitlab.com/qemu-project/qemu
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msix: Split PBA into it's own MemoryRegion
These don't have to be contiguous. Size them to only what they need and use separate MemoryRegions for the vector table and PBA. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Alex Williamson
Michael S. Tsirkin
parent
2cf62ad742
commit
d35e428c84
2 changed files with 73 additions and 43 deletions
106
hw/msix.c
106
hw/msix.c
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@ -37,7 +37,7 @@
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static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
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{
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uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
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uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
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MSIMessage msg;
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msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
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@ -93,7 +93,7 @@ static uint8_t msix_pending_mask(int vector)
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static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
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{
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return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
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return dev->msix_pba + vector / 8;
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}
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static int msix_is_pending(PCIDevice *dev, int vector)
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@ -114,7 +114,7 @@ static void msix_clr_pending(PCIDevice *dev, int vector)
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static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
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{
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unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
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return fmask || dev->msix_table[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
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}
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static bool msix_is_masked(PCIDevice *dev, int vector)
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@ -193,37 +193,47 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
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}
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}
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static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
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void *page = dev->msix_table_page;
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return pci_get_long(page + offset);
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return pci_get_long(dev->msix_table + addr);
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}
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static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
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int vector = offset / PCI_MSIX_ENTRY_SIZE;
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int vector = addr / PCI_MSIX_ENTRY_SIZE;
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bool was_masked;
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/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
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if (vector >= dev->msix_entries_nr) {
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return;
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}
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was_masked = msix_is_masked(dev, vector);
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pci_set_long(dev->msix_table_page + offset, val);
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pci_set_long(dev->msix_table + addr, val);
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msix_handle_mask_update(dev, vector, was_masked);
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}
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static const MemoryRegionOps msix_mmio_ops = {
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.read = msix_mmio_read,
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.write = msix_mmio_write,
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static const MemoryRegionOps msix_table_mmio_ops = {
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.read = msix_table_mmio_read,
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.write = msix_table_mmio_write,
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/* TODO: MSIX should be LITTLE_ENDIAN. */
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static uint64_t msix_pba_mmio_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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PCIDevice *dev = opaque;
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return pci_get_long(dev->msix_pba + addr);
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}
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static const MemoryRegionOps msix_pba_mmio_ops = {
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.read = msix_pba_mmio_read,
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/* TODO: MSIX should be LITTLE_ENDIAN. */
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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@ -236,11 +246,14 @@ static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
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{
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uint8_t *config = d->config + d->msix_cap;
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uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
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uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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uint32_t table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
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uint32_t pba = pci_get_long(config + PCI_MSIX_PBA);
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uint32_t pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
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/* TODO: for assigned devices, we'll want to make it possible to map
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* pending bits separately in case they are in a separate bar. */
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memory_region_add_subregion(bar, offset, &d->msix_mmio);
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memory_region_add_subregion(bar, table_offset, &d->msix_table_mmio);
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memory_region_add_subregion(bar, pba_offset, &d->msix_pba_mmio);
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}
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static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
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@ -252,7 +265,7 @@ static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
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vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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bool was_masked = msix_is_masked(dev, vector);
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dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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dev->msix_table[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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msix_handle_mask_update(dev, vector, was_masked);
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}
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}
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@ -264,6 +277,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size)
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{
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int ret;
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unsigned table_size, pba_size;
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/* Nothing to do if MSI is not supported by interrupt controller */
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if (!msi_supported) {
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@ -272,14 +286,20 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
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if (nentries > MSIX_MAX_ENTRIES)
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return -EINVAL;
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table_size = nentries * PCI_MSIX_ENTRY_SIZE;
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pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
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dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
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sizeof *dev->msix_entry_used);
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dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
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dev->msix_table = g_malloc0(table_size);
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dev->msix_pba = g_malloc0(pba_size);
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msix_mask_all(dev, nentries);
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memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
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"msix", MSIX_PAGE_SIZE);
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memory_region_init_io(&dev->msix_table_mmio, &msix_table_mmio_ops, dev,
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"msix-table", table_size);
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memory_region_init_io(&dev->msix_pba_mmio, &msix_pba_mmio_ops, dev,
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"msix-pba", pba_size);
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dev->msix_entries_nr = nentries;
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ret = msix_add_config(dev, nentries, bar_nr, bar_size);
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@ -292,9 +312,12 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries,
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err_config:
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dev->msix_entries_nr = 0;
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memory_region_destroy(&dev->msix_mmio);
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g_free(dev->msix_table_page);
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dev->msix_table_page = NULL;
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memory_region_destroy(&dev->msix_pba_mmio);
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g_free(dev->msix_pba);
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dev->msix_pba = NULL;
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memory_region_destroy(&dev->msix_table_mmio);
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g_free(dev->msix_table);
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dev->msix_table = NULL;
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g_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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return ret;
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@ -359,10 +382,14 @@ int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
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dev->msix_cap = 0;
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msix_free_irq_entries(dev);
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dev->msix_entries_nr = 0;
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memory_region_del_subregion(bar, &dev->msix_mmio);
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memory_region_destroy(&dev->msix_mmio);
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g_free(dev->msix_table_page);
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dev->msix_table_page = NULL;
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memory_region_del_subregion(bar, &dev->msix_pba_mmio);
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memory_region_destroy(&dev->msix_pba_mmio);
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g_free(dev->msix_pba);
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dev->msix_pba = NULL;
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memory_region_del_subregion(bar, &dev->msix_table_mmio);
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memory_region_destroy(&dev->msix_table_mmio);
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g_free(dev->msix_table);
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dev->msix_table = NULL;
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g_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
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@ -385,8 +412,8 @@ void msix_save(PCIDevice *dev, QEMUFile *f)
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return;
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}
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qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
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qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
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qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
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qemu_put_buffer(f, dev->msix_pba, (n + 7) / 8);
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}
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/* Should be called after restoring the config space. */
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@ -400,8 +427,8 @@ void msix_load(PCIDevice *dev, QEMUFile *f)
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}
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msix_free_irq_entries(dev);
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qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
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qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
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qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
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qemu_get_buffer(f, dev->msix_pba, (n + 7) / 8);
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msix_update_function_masked(dev);
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for (vector = 0; vector < n; vector++) {
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@ -448,7 +475,8 @@ void msix_reset(PCIDevice *dev)
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msix_free_irq_entries(dev);
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dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
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~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
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memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
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memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
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memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
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msix_mask_all(dev, dev->msix_entries_nr);
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}
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10
hw/pci.h
10
hw/pci.h
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@ -220,12 +220,14 @@ struct PCIDevice {
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/* MSI-X entries */
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int msix_entries_nr;
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/* Space to store MSIX table */
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uint8_t *msix_table_page;
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/* Space to store MSIX table & pending bit array */
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uint8_t *msix_table;
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uint8_t *msix_pba;
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/* MemoryRegion container for msix exclusive BAR setup */
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MemoryRegion msix_exclusive_bar;
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/* MMIO index used to map MSIX table and pending bit entries. */
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MemoryRegion msix_mmio;
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/* Memory Regions for MSIX table and pending bit entries. */
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MemoryRegion msix_table_mmio;
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MemoryRegion msix_pba_mmio;
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/* Reference-count for entries actually in use by driver. */
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unsigned *msix_entry_used;
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/* MSIX function mask set or MSIX disabled */
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