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target/riscv: Update check for Zca/Zcf/Zcd

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Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
version is higher than the priv version of C/F/D. So if we use check
for them instead of check for C/F/D totally, it will trigger new
problem when we try to disable the extensions based on the configured
priv version.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-05-17 10:57:09 -03:00 committed by Alistair Francis
parent 61a33ea95a
commit d33e39f995
4 changed files with 21 additions and 15 deletions
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12
target/riscv/insn_trans/trans_rvd.c.inc
View file

@ -31,9 +31,11 @@
} \
} while (0)
#define REQUIRE_ZCD(ctx) do { \
if (!ctx->cfg_ptr->ext_zcd) { \
return false; \
#define REQUIRE_ZCD_OR_DC(ctx) do { \
if (!ctx->cfg_ptr->ext_zcd) { \
if (!has_ext(ctx, RVD) || !has_ext(ctx, RVC)) { \
return false; \
} \
} \
} while (0)
@ -67,13 +69,13 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
{
REQUIRE_ZCD(ctx);
REQUIRE_ZCD_OR_DC(ctx);
return trans_fld(ctx, a);
}
static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
{
REQUIRE_ZCD(ctx);
REQUIRE_ZCD_OR_DC(ctx);
return trans_fsd(ctx, a);
}

14
target/riscv/insn_trans/trans_rvf.c.inc
View file

@ -30,10 +30,12 @@
} \
} while (0)
#define REQUIRE_ZCF(ctx) do { \
if (!ctx->cfg_ptr->ext_zcf) { \
return false; \
} \
#define REQUIRE_ZCF_OR_FC(ctx) do { \
if (!ctx->cfg_ptr->ext_zcf) { \
if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \
return false; \
} \
} \
} while (0)
static bool trans_flw(DisasContext *ctx, arg_flw *a)
@ -69,13 +71,13 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
{
REQUIRE_ZCF(ctx);
REQUIRE_ZCF_OR_FC(ctx);
return trans_flw(ctx, a);
}
static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
{
REQUIRE_ZCF(ctx);
REQUIRE_ZCF_OR_FC(ctx);
return trans_fsw(ctx, a);
}

5
target/riscv/insn_trans/trans_rvi.c.inc
View file

@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
gen_set_pc(ctx, cpu_pc);
if (!ctx->cfg_ptr->ext_zca) {
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
TCGv t0 = tcg_temp_new();
misaligned = gen_new_label();
@ -169,7 +169,8 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_set_label(l); /* branch taken */
if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) {
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca &&
((ctx->base.pc_next + a->imm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {

5
target/riscv/translate.c
View file

@ -551,7 +551,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
if (!ctx->cfg_ptr->ext_zca) {
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@ -1125,7 +1125,8 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
* The Zca extension is added as way to refer to instructions in the C
* extension that do not include the floating-point loads and stores
*/
if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) {
if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) &&
decode_insn16(ctx, opcode)) {
return;
}
} else {