system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-09-20 19:21:31 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/mips: Define R5900 MMI<0|1|2|3> subclasses and opcode constants

Browse source 
Define MMI0, MMI1, MMI2, MMI3 subclass opcodes, and other opcodes of
instructions in MMI class.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Fredrik Noring 2018-10-21 17:33:32 +02:00 committed by Aleksandar Markovic
parent f99c0d6da3
commit d329721172
1 changed files with 51 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

51
target/mips/translate.c
View file

@ -2129,6 +2129,57 @@ enum {
TX79_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
/*
* TX79 Multimedia Instructions with opcode field = MMI:
*
* 31 26 5 0
* +--------+-------------------------------+--------+
* | MMI | |function|
* +--------+-------------------------------+--------+
*
* function bits 2..0
* bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
* 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
* -------+-------+-------+-------+-------+-------+-------+-------+-------
* 0 000 | MADD | MADDU | * | * | PLZCW | * | * | *
* 1 001 | MMI0% | MMI2% | * | * | * | * | * | *
* 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | *
* 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | *
* 4 100 | MADD1 | MADDU1| * | * | * | * | * | *
* 5 101 | MMI1% | MMI3% | * | * | * | * | * | *
* 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH
* 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
*/
#define MASK_TX79_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
enum {
TX79_MMI_MADD = 0x00 | TX79_CLASS_MMI, /* Same as OPC_MADD */
TX79_MMI_MADDU = 0x01 | TX79_CLASS_MMI, /* Same as OPC_MADDU */
TX79_MMI_PLZCW = 0x04 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI0 = 0x08 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI2 = 0x09 | TX79_CLASS_MMI,
TX79_MMI_MFHI1 = 0x10 | TX79_CLASS_MMI, /* Same minor as OPC_MFHI */
TX79_MMI_MTHI1 = 0x11 | TX79_CLASS_MMI, /* Same minor as OPC_MTHI */
TX79_MMI_MFLO1 = 0x12 | TX79_CLASS_MMI, /* Same minor as OPC_MFLO */
TX79_MMI_MTLO1 = 0x13 | TX79_CLASS_MMI, /* Same minor as OPC_MTLO */
TX79_MMI_MULT1 = 0x18 | TX79_CLASS_MMI, /* Same minor as OPC_MULT */
TX79_MMI_MULTU1 = 0x19 | TX79_CLASS_MMI, /* Same minor as OPC_MULTU */
TX79_MMI_DIV1 = 0x1A | TX79_CLASS_MMI, /* Same minor as OPC_DIV */
TX79_MMI_DIVU1 = 0x1B | TX79_CLASS_MMI, /* Same minor as OPC_DIVU */
TX79_MMI_MADD1 = 0x20 | TX79_CLASS_MMI,
TX79_MMI_MADDU1 = 0x21 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI1 = 0x28 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI3 = 0x29 | TX79_CLASS_MMI,
TX79_MMI_PMFHL = 0x30 | TX79_CLASS_MMI,
TX79_MMI_PMTHL = 0x31 | TX79_CLASS_MMI,
TX79_MMI_PSLLH = 0x34 | TX79_CLASS_MMI,
TX79_MMI_PSRLH = 0x36 | TX79_CLASS_MMI,
TX79_MMI_PSRAH = 0x37 | TX79_CLASS_MMI,
TX79_MMI_PSLLW = 0x3C | TX79_CLASS_MMI,
TX79_MMI_PSRLW = 0x3E | TX79_CLASS_MMI,
TX79_MMI_PSRAW = 0x3F | TX79_CLASS_MMI,
};
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];