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target/arm: Introduce and use read_fp_hreg
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 3d99d93126
)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit is contained in:
parent
7c38f3703d
commit
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@ -614,6 +614,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
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return v;
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return v;
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}
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}
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static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
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{
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TCGv_i32 v = tcg_temp_new_i32();
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tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
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return v;
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}
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/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
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/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
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* If SVE is not enabled, then there are only 128 bits in the vector.
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* If SVE is not enabled, then there are only 128 bits in the vector.
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*/
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*/
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@ -4638,11 +4646,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
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static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
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static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
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{
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{
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TCGv_ptr fpst = NULL;
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TCGv_ptr fpst = NULL;
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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TCGv_i32 tcg_op = read_fp_hreg(s, rn);
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
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switch (opcode) {
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switch (opcode) {
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case 0x0: /* FMOV */
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case 0x0: /* FMOV */
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tcg_gen_mov_i32(tcg_res, tcg_op);
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tcg_gen_mov_i32(tcg_res, tcg_op);
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@ -7538,13 +7544,10 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_op2);
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tcg_temp_free_i64(tcg_op2);
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tcg_temp_free_i64(tcg_res);
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tcg_temp_free_i64(tcg_res);
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} else {
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} else {
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TCGv_i32 tcg_op1 = tcg_temp_new_i32();
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TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
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TCGv_i32 tcg_op2 = tcg_temp_new_i32();
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TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
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TCGv_i64 tcg_res = tcg_temp_new_i64();
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TCGv_i64 tcg_res = tcg_temp_new_i64();
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read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
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read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
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gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
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gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
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gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
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gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
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@ -8085,13 +8088,10 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
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fpst = get_fpstatus_ptr(true);
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fpst = get_fpstatus_ptr(true);
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tcg_op1 = tcg_temp_new_i32();
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tcg_op1 = read_fp_hreg(s, rn);
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tcg_op2 = tcg_temp_new_i32();
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tcg_op2 = read_fp_hreg(s, rm);
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tcg_res = tcg_temp_new_i32();
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tcg_res = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
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read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
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switch (fpopcode) {
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switch (fpopcode) {
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case 0x03: /* FMULX */
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case 0x03: /* FMULX */
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gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
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gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
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@ -12010,11 +12010,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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}
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}
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if (is_scalar) {
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if (is_scalar) {
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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TCGv_i32 tcg_op = read_fp_hreg(s, rn);
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
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switch (fpop) {
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switch (fpop) {
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case 0x1a: /* FCVTNS */
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1b: /* FCVTMS */
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