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target/arm: Convert T16 load/store (register offset)

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-48-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:37 -07:00 committed by Peter Maydell
parent 080c4eadcb
commit d1d229179c
2 changed files with 17 additions and 49 deletions
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15
target/arm/t16.decode
View file

@ -23,6 +23,7 @@
&s_rrr_shr !extern s rn rd rm rs shty
&s_rri_rot !extern s rn rd imm rot
&s_rrrr !extern s rd rn rm ra
&ldst_rr !extern p w u rn rt rm shimm shtype
# Set S if the instruction is outside of an IT block.
%s !function=t16_setflags
@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_noshr
MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
BIC_rrri 010000 1110 ... ... @lll_noshr
MVN_rxri 010000 1111 ... ... @lll_noshr
# Load/store (register offset)
@ldst_rr ....... rm:3 rn:3 rt:3 \
&ldst_rr p=1 w=0 u=1 shimm=0 shtype=0
STR_rr 0101 000 ... ... ... @ldst_rr
STRH_rr 0101 001 ... ... ... @ldst_rr
STRB_rr 0101 010 ... ... ... @ldst_rr
LDRSB_rr 0101 011 ... ... ... @ldst_rr
LDR_rr 0101 100 ... ... ... @ldst_rr
LDRH_rr 0101 101 ... ... ... @ldst_rr
LDRB_rr 0101 110 ... ... ... @ldst_rr
LDRSH_rr 0101 111 ... ... ... @ldst_rr

51
target/arm/translate.c
View file

@ -10864,55 +10864,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
case 5:
/* load/store register offset. */
rd = insn & 7;
rn = (insn >> 3) & 7;
rm = (insn >> 6) & 7;
op = (insn >> 9) & 7;
addr = load_reg(s, rn);
tmp = load_reg(s, rm);
tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp);
if (op < 3) { /* store */
tmp = load_reg(s, rd);
} else {
tmp = tcg_temp_new_i32();
}
switch (op) {
case 0: /* str */
gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
case 1: /* strh */
gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
case 2: /* strb */
gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
case 3: /* ldrsb */
gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
case 4: /* ldr */
gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
case 5: /* ldrh */
gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
case 6: /* ldrb */
gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
case 7: /* ldrsh */
gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit);
break;
}
if (op >= 3) { /* load */
store_reg(s, rd, tmp);
} else {
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
break;
/* load/store register offset, in decodetree */
goto illegal_op;
case 6:
/* load/store word immediate offset */