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tcg/s390: Split out constraint sets to tcg-target-con-set.h
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
665be288ac
commit
d1c36a9032
3 changed files with 81 additions and 70 deletions
29
tcg/s390/tcg-target-con-set.h
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29
tcg/s390/tcg-target-con-set.h
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@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define S390 target-specific constraint sets.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(L, L)
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C_O0_I2(r, r)
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C_O0_I2(r, ri)
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C_O1_I1(r, L)
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C_O1_I1(r, r)
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C_O1_I2(r, 0, ri)
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C_O1_I2(r, 0, rI)
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C_O1_I2(r, 0, rJ)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, rZ, r)
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C_O1_I4(r, r, ri, r, 0)
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C_O1_I4(r, r, ri, rI, 0)
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C_O2_I2(b, a, 0, r)
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C_O2_I3(b, a, 0, 1, r)
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C_O2_I4(r, r, 0, 1, rA, r)
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C_O2_I4(r, r, 0, 1, ri, r)
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C_O2_I4(r, r, 0, 1, r, r)
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@ -2274,27 +2274,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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}
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static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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{
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static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
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static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
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static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
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static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
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static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
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static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
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static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
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static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
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static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
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static const TCGTargetOpDef a2_r
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= { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
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static const TCGTargetOpDef a2_ri
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= { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
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static const TCGTargetOpDef a2_rA
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= { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
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switch (op) {
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case INDEX_op_goto_ptr:
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return &r;
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return C_O0_I1(r);
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case INDEX_op_ld8u_i32:
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case INDEX_op_ld8u_i64:
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@ -2308,6 +2292,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_ld32u_i64:
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case INDEX_op_ld32s_i64:
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case INDEX_op_ld_i64:
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return C_O1_I1(r, r);
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case INDEX_op_st8_i32:
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case INDEX_op_st8_i64:
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case INDEX_op_st16_i32:
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@ -2315,11 +2301,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_st_i32:
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case INDEX_op_st32_i64:
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case INDEX_op_st_i64:
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return &r_r;
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return C_O0_I2(r, r);
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case INDEX_op_add_i32:
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case INDEX_op_add_i64:
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return &r_r_ri;
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case INDEX_op_shl_i64:
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case INDEX_op_shr_i64:
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case INDEX_op_sar_i64:
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case INDEX_op_rotl_i32:
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case INDEX_op_rotl_i64:
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case INDEX_op_rotr_i32:
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case INDEX_op_rotr_i64:
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case INDEX_op_clz_i64:
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case INDEX_op_setcond_i32:
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case INDEX_op_setcond_i64:
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return C_O1_I2(r, r, ri);
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case INDEX_op_sub_i32:
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case INDEX_op_sub_i64:
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case INDEX_op_and_i32:
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@ -2328,35 +2325,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_or_i64:
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case INDEX_op_xor_i32:
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case INDEX_op_xor_i64:
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return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
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return (s390_facilities & FACILITY_DISTINCT_OPS
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? C_O1_I2(r, r, ri)
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: C_O1_I2(r, 0, ri));
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case INDEX_op_mul_i32:
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/* If we have the general-instruction-extensions, then we have
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MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
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have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
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return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
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return (s390_facilities & FACILITY_GEN_INST_EXT
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? C_O1_I2(r, 0, ri)
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: C_O1_I2(r, 0, rI));
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case INDEX_op_mul_i64:
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return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
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return (s390_facilities & FACILITY_GEN_INST_EXT
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? C_O1_I2(r, 0, rJ)
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: C_O1_I2(r, 0, rI));
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case INDEX_op_shl_i32:
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case INDEX_op_shr_i32:
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case INDEX_op_sar_i32:
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return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
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case INDEX_op_shl_i64:
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case INDEX_op_shr_i64:
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case INDEX_op_sar_i64:
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return &r_r_ri;
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case INDEX_op_rotl_i32:
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case INDEX_op_rotl_i64:
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case INDEX_op_rotr_i32:
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case INDEX_op_rotr_i64:
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return &r_r_ri;
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return (s390_facilities & FACILITY_DISTINCT_OPS
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? C_O1_I2(r, r, ri)
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: C_O1_I2(r, 0, ri));
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i64:
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return &r_ri;
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return C_O0_I2(r, ri);
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case INDEX_op_bswap16_i32:
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case INDEX_op_bswap16_i64:
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@ -2379,63 +2374,49 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_extu_i32_i64:
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case INDEX_op_extract_i32:
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case INDEX_op_extract_i64:
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return &r_r;
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case INDEX_op_clz_i64:
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case INDEX_op_setcond_i32:
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case INDEX_op_setcond_i64:
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return &r_r_ri;
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return C_O1_I1(r, r);
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case INDEX_op_qemu_ld_i32:
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case INDEX_op_qemu_ld_i64:
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return &r_L;
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return C_O1_I1(r, L);
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case INDEX_op_qemu_st_i64:
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case INDEX_op_qemu_st_i32:
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return &L_L;
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return C_O0_I2(L, L);
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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{
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static const TCGTargetOpDef dep
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= { .args_ct_str = { "r", "rZ", "r" } };
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return &dep;
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}
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return C_O1_I2(r, rZ, r);
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case INDEX_op_movcond_i32:
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case INDEX_op_movcond_i64:
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{
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static const TCGTargetOpDef movc
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= { .args_ct_str = { "r", "r", "ri", "r", "0" } };
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static const TCGTargetOpDef movc_l
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= { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
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return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
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}
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return (s390_facilities & FACILITY_LOAD_ON_COND2
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? C_O1_I4(r, r, ri, rI, 0)
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: C_O1_I4(r, r, ri, r, 0));
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case INDEX_op_div2_i32:
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case INDEX_op_div2_i64:
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case INDEX_op_divu2_i32:
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case INDEX_op_divu2_i64:
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{
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static const TCGTargetOpDef div2
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= { .args_ct_str = { "b", "a", "0", "1", "r" } };
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return &div2;
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}
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return C_O2_I3(b, a, 0, 1, r);
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case INDEX_op_mulu2_i64:
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{
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static const TCGTargetOpDef mul2
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= { .args_ct_str = { "b", "a", "0", "r" } };
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return &mul2;
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}
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return C_O2_I2(b, a, 0, r);
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case INDEX_op_add2_i32:
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case INDEX_op_sub2_i32:
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return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
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return (s390_facilities & FACILITY_EXT_IMM
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? C_O2_I4(r, r, 0, 1, ri, r)
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: C_O2_I4(r, r, 0, 1, r, r));
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case INDEX_op_add2_i64:
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case INDEX_op_sub2_i64:
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return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
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return (s390_facilities & FACILITY_EXT_IMM
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? C_O2_I4(r, r, 0, 1, rA, r)
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: C_O2_I4(r, r, 0, 1, r, r));
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default:
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break;
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g_assert_not_reached();
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}
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return NULL;
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}
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static void query_s390_facilities(void)
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@ -159,5 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
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#define TCG_TARGET_NEED_LDST_LABELS
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#endif
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#define TCG_TARGET_NEED_POOL_LABELS
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#define TCG_TARGET_CON_SET_H
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#endif
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