system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-11-05 20:35:44 +00:00
Code Issues Projects Releases Packages Wiki Activity

SPARC64: implement addtional MMU faults related to nonfaulting load

Browse source 
This patch implements MMU faults caused by TTE.NFO and TTE.E:
- access other than nonfaulting load to a page marked NFO should
  raise data_access_exception
- nonfaulting load to a page marked with E bit should raise
  data_access_exception

To distinguish nonfaulting loads, this patch extends (abuses?) the rw
argument of get_physical_address_data().  rw is set to 4 on nonfaulting
loads.

Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Tsuneo Saito 2011-07-22 00:16:33 +09:00 committed by Blue Swirl
parent b7785d2072
commit d1afc48b7c
2 changed files with 30 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
target-sparc/cpu.h
View file

@ -290,15 +290,19 @@ enum {
#endif
#define TTE_VALID_BIT (1ULL << 63)
#define TTE_NFO_BIT (1ULL << 60)
#define TTE_USED_BIT (1ULL << 41)
#define TTE_LOCKED_BIT (1ULL << 6)
#define TTE_SIDEEFFECT_BIT (1ULL << 3)
#define TTE_PRIV_BIT (1ULL << 2)
#define TTE_W_OK_BIT (1ULL << 1)
#define TTE_GLOBAL_BIT (1ULL << 0)
#define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
#define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT)
#define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
#define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
#define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT)
#define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT)
#define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)

29
target-sparc/helper.c
View file

@ -445,27 +445,50 @@ static int get_physical_address_data(CPUState *env,
if (rw == 1) {
sfsr |= SFSR_WRITE_BIT;
} else if (rw == 4) {
sfsr |= SFSR_NF_BIT;
}
for (i = 0; i < 64; i++) {
// ctx match, vaddr match, valid?
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
int do_fault = 0;
// access ok?
/* multiple bits in SFSR.FT may be set on TT_DFAULT */
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
do_fault = 1;
sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
env->exception_index = TT_DFAULT;
DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
" mmu_idx=%d tl=%d\n",
address, context, mmu_idx, env->tl);
}
if (rw == 4) {
if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
do_fault = 1;
sfsr |= SFSR_FT_NF_E_BIT;
}
} else {
if (TTE_IS_NFO(env->dtlb[i].tte)) {
do_fault = 1;
sfsr |= SFSR_FT_NFO_BIT;
}
}
if (do_fault) {
/* faults above are reported with TT_DFAULT. */
env->exception_index = TT_DFAULT;
} else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
do_fault = 1;
env->exception_index = TT_DPROT;
DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
" mmu_idx=%d tl=%d\n",
address, context, mmu_idx, env->tl);
} else {
}
if (!do_fault) {
*prot = PAGE_READ;
if (TTE_IS_W_OK(env->dtlb[i].tte)) {
*prot |= PAGE_WRITE;
@ -752,7 +775,7 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
{
target_phys_addr_t phys_addr;
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
return -1;
}
return phys_addr;