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tcg-ia64: Move AREG0 to R32

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Since the move away from the global areg0, we're no longer globally
reserving areg0.  Which means our use of R7 clobbers a call-saved
register.  Shift areg0 into the windowed registers.  Indeed, choose
the incoming parameter register that it comes to us by.

This requires moving the register holding the return address elsewhere.
Choose R33 for tidiness.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-09-05 14:45:54 -04:00
parent 6d264b38fc
commit d15de15ca0
2 changed files with 8 additions and 9 deletions
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13
tcg/ia64/tcg-target.c
View file

@ -109,7 +109,6 @@ enum {
};
static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R33,
TCG_REG_R35,
TCG_REG_R36,
TCG_REG_R37,
@ -2404,8 +2403,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_bundle(s, miI,
tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
TCG_REG_R34, 32, 24, 0),
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
TCG_AREG0, 0, TCG_REG_R32),
INSN_NOP_I,
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
TCG_REG_B6, TCG_REG_R33, 0));
@ -2424,7 +2422,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
TCG_REG_R12, -frame_size, TCG_REG_R12),
tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
TCG_REG_R32, TCG_REG_B0),
TCG_REG_R33, TCG_REG_B0),
tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
/* epilogue */
@ -2432,7 +2430,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_bundle(s, miI,
INSN_NOP_M,
tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
TCG_REG_B0, TCG_REG_R32, 0),
TCG_REG_B0, TCG_REG_R33, 0),
tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
TCG_REG_R12, frame_size, TCG_REG_R12));
tcg_out_bundle(s, miB,
@ -2489,16 +2487,17 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* return address */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
/* The following 3 are not in use, are call-saved, but *not* saved
/* The following 4 are not in use, are call-saved, but *not* saved
by the prologue. Therefore we cannot use them without modifying
the prologue. There doesn't seem to be any good reason to use
these as opposed to the windowed registers. */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7);
tcg_add_target_add_op_defs(ia64_op_defs);
}

4
tcg/ia64/tcg-target.h
View file

@ -92,6 +92,8 @@ typedef enum {
TCG_REG_R61,
TCG_REG_R62,
TCG_REG_R63,
TCG_AREG0 = TCG_REG_R32,
} TCGReg;
#define TCG_CT_CONST_ZERO 0x100
@ -162,8 +164,6 @@ typedef enum {
#define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */
#define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */
#define TCG_AREG0 TCG_REG_R7
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
start = start & ~(32UL - 1UL);