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target/arm: Implement vector shifted FCVT for fp16
While we have some of the scalar paths for FCVT for fp16, we failed to decode the fp16 version of these instructions. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180502221552.3873-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -7448,19 +7448,28 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
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bool is_q, bool is_u,
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bool is_q, bool is_u,
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int immh, int immb, int rn, int rd)
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int immh, int immb, int rn, int rd)
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{
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{
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bool is_double = extract32(immh, 3, 1);
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int immhb = immh << 3 | immb;
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int immhb = immh << 3 | immb;
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int fracbits = (is_double ? 128 : 64) - immhb;
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int pass, size, fracbits;
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int pass;
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TCGv_ptr tcg_fpstatus;
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TCGv_ptr tcg_fpstatus;
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TCGv_i32 tcg_rmode, tcg_shift;
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TCGv_i32 tcg_rmode, tcg_shift;
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if (!extract32(immh, 2, 2)) {
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if (immh & 0x8) {
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unallocated_encoding(s);
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size = MO_64;
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return;
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if (!is_scalar && !is_q) {
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}
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unallocated_encoding(s);
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return;
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if (!is_scalar && !is_q && is_double) {
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}
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} else if (immh & 0x4) {
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size = MO_32;
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} else if (immh & 0x2) {
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size = MO_16;
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if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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unallocated_encoding(s);
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return;
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}
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} else {
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/* Should have split out AdvSIMD modified immediate earlier. */
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assert(immh == 1);
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unallocated_encoding(s);
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unallocated_encoding(s);
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return;
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return;
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}
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}
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@ -7472,11 +7481,12 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
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assert(!(is_scalar && is_q));
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assert(!(is_scalar && is_q));
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tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
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tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
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tcg_fpstatus = get_fpstatus_ptr(false);
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tcg_fpstatus = get_fpstatus_ptr(size == MO_16);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
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gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
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fracbits = (16 << size) - immhb;
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tcg_shift = tcg_const_i32(fracbits);
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tcg_shift = tcg_const_i32(fracbits);
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if (is_double) {
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if (size == MO_64) {
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int maxpass = is_scalar ? 1 : 2;
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int maxpass = is_scalar ? 1 : 2;
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for (pass = 0; pass < maxpass; pass++) {
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for (pass = 0; pass < maxpass; pass++) {
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@ -7493,20 +7503,37 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
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}
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}
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clear_vec_high(s, is_q, rd);
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clear_vec_high(s, is_q, rd);
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} else {
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} else {
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int maxpass = is_scalar ? 1 : is_q ? 4 : 2;
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void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
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int maxpass = is_scalar ? 1 : ((8 << is_q) >> size);
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switch (size) {
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case MO_16:
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if (is_u) {
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fn = gen_helper_vfp_toulh;
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} else {
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fn = gen_helper_vfp_toslh;
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}
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break;
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case MO_32:
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if (is_u) {
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fn = gen_helper_vfp_touls;
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} else {
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fn = gen_helper_vfp_tosls;
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}
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break;
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default:
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g_assert_not_reached();
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}
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for (pass = 0; pass < maxpass; pass++) {
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for (pass = 0; pass < maxpass; pass++) {
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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TCGv_i32 tcg_op = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_op, rn, pass, size);
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if (is_u) {
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fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
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gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
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} else {
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gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
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}
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if (is_scalar) {
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if (is_scalar) {
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write_fp_sreg(s, rd, tcg_op);
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write_fp_sreg(s, rd, tcg_op);
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} else {
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} else {
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write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
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write_vec_element_i32(s, tcg_op, rd, pass, size);
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}
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}
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tcg_temp_free_i32(tcg_op);
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tcg_temp_free_i32(tcg_op);
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}
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}
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