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Hexagon (target/hexagon) Short-circuit more HVX single instruction packets
The generated helpers for HVX use pass-by-reference, so they can't short-circuit when the reads/writes overlap. The instructions with overrides are OK because they use tcg_gen_gvec_*. We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs to set the flag when the instruction is an HVX instruction with a generated helper. We add an override for V6_vcombine so that it can be short-circuited along with a test case in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>
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@ -212,6 +212,11 @@ def gen_analyze_func(f, tag, regs, imms):
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if has_generated_helper and "A_SCALAR_LOAD" in hex_common.attribdict[tag]:
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f.write(" ctx->need_pkt_has_store_s1 = true;\n")
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## Mark HVX instructions with generated helpers
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if (has_generated_helper and
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"A_CVI" in hex_common.attribdict[tag]):
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f.write(" ctx->has_hvx_helper = true;\n")
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f.write("}\n\n")
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@ -140,6 +140,29 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
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sizeof(MMVector), sizeof(MMVector)); \
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} while (0)
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/*
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* Vector combine
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*
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* Be careful that the source and dest don't overlap
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*/
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#define fGEN_TCG_V6_vcombine(SHORTCODE) \
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do { \
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if (VddV_off != VuV_off) { \
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tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), VuV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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} else { \
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intptr_t tmpoff = offsetof(CPUHexagonState, vtmp); \
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tcg_gen_gvec_mov(MO_64, tmpoff, VuV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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tcg_gen_gvec_mov(MO_64, VddV_off, VvV_off, \
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sizeof(MMVector), sizeof(MMVector)); \
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tcg_gen_gvec_mov(MO_64, VddV_off + sizeof(MMVector), tmpoff, \
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sizeof(MMVector), sizeof(MMVector)); \
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} \
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} while (0)
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/* Vector conditional move */
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#define fGEN_TCG_VEC_CMOV(PRED) \
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do { \
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@ -378,8 +378,20 @@ static bool need_commit(DisasContext *ctx)
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return true;
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}
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if (pkt->num_insns == 1 && !pkt->pkt_has_hvx) {
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return false;
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if (pkt->num_insns == 1) {
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if (pkt->pkt_has_hvx) {
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/*
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* The HVX instructions with generated helpers use
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* pass-by-reference, so they need the read/write overlap
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* check below.
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* The HVX instructions with overrides are OK.
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*/
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if (!ctx->has_hvx_helper) {
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return false;
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}
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} else {
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return false;
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}
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}
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/* Check for overlap between register reads and writes */
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@ -454,6 +466,7 @@ static void analyze_packet(DisasContext *ctx)
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{
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Packet *pkt = ctx->pkt;
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ctx->need_pkt_has_store_s1 = false;
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ctx->has_hvx_helper = false;
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for (int i = 0; i < pkt->num_insns; i++) {
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Insn *insn = &pkt->insn[i];
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ctx->insn = insn;
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@ -68,6 +68,7 @@ typedef struct DisasContext {
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bool is_tight_loop;
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bool need_pkt_has_store_s1;
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bool short_circuit;
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bool has_hvx_helper;
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} DisasContext;
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static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
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@ -454,6 +454,25 @@ static void test_load_cur_predicated(void)
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check_output_w(__LINE__, BUFSIZE);
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}
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static void test_vcombine(void)
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{
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for (int i = 0; i < BUFSIZE / 2; i++) {
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asm volatile("v2 = vsplat(%0)\n\t"
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"v3 = vsplat(%1)\n\t"
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"v3:2 = vcombine(v2, v3)\n\t"
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"vmem(%2+#0) = v2\n\t"
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"vmem(%2+#1) = v3\n\t"
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:
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: "r"(2 * i), "r"(2 * i + 1), "r"(&output[2 * i])
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: "v2", "v3", "memory");
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
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expect[2 * i].w[j] = 2 * i + 1;
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expect[2 * i + 1].w[j] = 2 * i;
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}
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}
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check_output_w(__LINE__, BUFSIZE);
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}
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int main()
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{
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init_buffers();
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@ -494,6 +513,8 @@ int main()
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test_load_tmp_predicated();
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test_load_cur_predicated();
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test_vcombine();
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puts(err ? "FAIL" : "PASS");
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return err ? 1 : 0;
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}
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