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Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging

Pull request

# gpg: Signature made Tue 17 Mar 2020 23:22:33 GMT
# gpg:                using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full]
# Primary key fingerprint: FAEB 9711 A12C F475 812F  18F2 88A9 064D 1835 61EB
#      Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76  CBD0 7DEF 8106 AAFC 390E

* remotes/jnsnow/tags/ide-pull-request:
  hw/ide: Remove unneeded inclusion of hw/ide.h
  hw/ide: Move MAX_IDE_DEVS define to hw/ide/internal.h
  hw/ide: Do ide_drive_get() within pci_ide_create_devs()
  hw/ide/pci.c: Coding style update to fix checkpatch errors
  hw/ide: Remove now unneded #include "hw/pci/pci.h" from hw/ide.h
  hw/ide: Get rid of piix4_init function
  hw/isa/piix4.c: Introduce variable to store devfn
  hw/ide: Get rid of piix3_init functions
  hd-geo-test: Clean up use of buf[] in create_qcow2_with_mbr()
  via-ide: always use legacy IRQ 14/15 routing
  via-ide: allow guests to write to PCI_CLASS_PROG
  via-ide: initialise IDE controller in legacy mode
  via-ide: ensure that PCI_INTERRUPT_LINE is hard-wired to its default value
  pci: Honour wmask when resetting PCI_INTERRUPT_LINE
  ide/via: Get rid of via_ide_init()
  via-ide: move registration of VMStateDescription to DeviceClass
  cmd646: remove unused pci_cmd646_ide_init() function
  dp264: use pci_create_simple() to initialise the cmd646 device
  cmd646: register vmstate_ide_pci VMStateDescription in DeviceClass
  cmd646: register cmd646_reset() function in DeviceClass

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-03-19 11:14:24 +00:00
parent f57587c7d4 7d0776ca7f
commit ce73691e25
24 changed files with 61 additions and 127 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
hw/alpha/dp264.c
View file

@ -15,7 +15,7 @@
#include "qemu/error-report.h"
#include "sysemu/sysemu.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/timer/i8254.h"
#include "hw/isa/superio.h"
#include "hw/dma/i8257.h"
@ -57,6 +57,7 @@ static void clipper_init(MachineState *machine)
const char *initrd_filename = machine->initrd_filename;
AlphaCPU *cpus[4];
PCIBus *pci_bus;
PCIDevice *pci_dev;
ISABus *isa_bus;
qemu_irq rtc_irq;
long size, i;
@ -99,12 +100,8 @@ static void clipper_init(MachineState *machine)
isa_create_simple(isa_bus, TYPE_SMC37C669_SUPERIO);
/* IDE disk setup. */
{
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_cmd646_ide_init(pci_bus, hd, 0);
}
pci_dev = pci_create_simple(pci_bus, -1, "cmd646-ide");
pci_ide_create_devs(pci_dev);
/* Load PALcode. Given that this is not "real" cpu palcode,
but one explicitly written for the emulation, we might as

1
hw/hppa/hppa_sys.h
View file

@ -5,7 +5,6 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/ide.h"
#include "hw/boards.h"
#include "hw/intc/i8259.h"

1
hw/hppa/machine.c
View file

@ -13,7 +13,6 @@
#include "sysemu/reset.h"
#include "sysemu/sysemu.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/ide.h"
#include "hw/timer/i8254.h"
#include "hw/char/serial.h"
#include "hw/net/lasi_82596.h"

18
hw/i386/pc_piix.c
View file

@ -38,7 +38,7 @@
#include "hw/pci/pci_ids.h"
#include "hw/usb.h"
#include "net/net.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/irq.h"
#include "sysemu/kvm.h"
#include "hw/kvm/clock.h"
@ -85,7 +85,6 @@ static void pc_init1(MachineState *machine,
int piix3_devfn = -1;
qemu_irq smi_irq;
GSIState *gsi_state;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
MemoryRegion *ram_memory;
@ -239,21 +238,22 @@ static void pc_init1(MachineState *machine,
pc_nic_init(pcmc, isa_bus, pci_bus);
ide_drive_get(hd, ARRAY_SIZE(hd));
if (pcmc->pci_enabled) {
PCIDevice *dev;
if (xen_enabled()) {
dev = pci_piix3_xen_ide_init(pci_bus, hd, piix3_devfn + 1);
} else {
dev = pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
}
dev = pci_create_simple(pci_bus, piix3_devfn + 1,
xen_enabled() ? "piix3-ide-xen" : "piix3-ide");
pci_ide_create_devs(dev);
idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
}
#ifdef CONFIG_IDE_ISA
else {
else {
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
int i;
ide_drive_get(hd, ARRAY_SIZE(hd));
for (i = 0; i < MAX_IDE_BUS; i++) {
ISADevice *dev;
char busname[] = "ide.0";

1
hw/ide/ahci_internal.h
View file

@ -27,6 +27,7 @@
#include "hw/ide/ahci.h"
#include "hw/ide/internal.h"
#include "hw/sysbus.h"
#include "hw/pci/pci.h"
#define AHCI_MEM_BAR_SIZE 0x1000
#define AHCI_MAX_PORTS 32

21
hw/ide/cmd646.c
View file

@ -207,9 +207,9 @@ static void cmd646_set_irq(void *opaque, int channel, int level)
cmd646_update_irq(pd);
}
static void cmd646_reset(void *opaque)
static void cmd646_reset(DeviceState *dev)
{
PCIIDEState *d = opaque;
PCIIDEState *d = PCI_IDE(dev);
unsigned int i;
for (i = 0; i < 2; i++) {
@ -301,9 +301,6 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
ide_register_restart_cb(&d->bus[i]);
}
g_free(irq);
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
qemu_register_reset(cmd646_reset, d);
}
static void pci_cmd646_ide_exitfn(PCIDevice *dev)
@ -317,18 +314,6 @@ static void pci_cmd646_ide_exitfn(PCIDevice *dev)
}
}
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
int secondary_ide_enabled)
{
PCIDevice *dev;
dev = pci_create(bus, -1, "cmd646-ide");
qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
qdev_init_nofail(&dev->qdev);
pci_ide_create_devs(dev, hd_table);
}
static Property cmd646_ide_properties[] = {
DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
DEFINE_PROP_END_OF_LIST(),
@ -339,6 +324,8 @@ static void cmd646_ide_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->reset = cmd646_reset;
dc->vmsd = &vmstate_ide_pci;
k->realize = pci_cmd646_ide_realize;
k->exit = pci_cmd646_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_CMD;

11
hw/ide/pci.c
View file

@ -476,17 +476,20 @@ const VMStateDescription vmstate_ide_pci = {
}
};
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
/* hd_table must contain 4 block drivers */
void pci_ide_create_devs(PCIDevice *dev)
{
PCIIDEState *d = PCI_IDE(dev);
DriveInfo *hd_table[2 * MAX_IDE_DEVS];
static const int bus[4] = { 0, 0, 1, 1 };
static const int unit[4] = { 0, 1, 0, 1 };
int i;
ide_drive_get(hd_table, ARRAY_SIZE(hd_table));
for (i = 0; i < 4; i++) {
if (hd_table[i] == NULL)
continue;
ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
if (hd_table[i]) {
ide_create_drive(d->bus + bus[i], unit[i], hd_table[i]);
}
}
}

31
hw/ide/piix.c
View file

@ -197,15 +197,6 @@ int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux)
return 0;
}
PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
PCIDevice *dev;
dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
pci_ide_create_devs(dev, hd_table);
return dev;
}
static void pci_piix_ide_exitfn(PCIDevice *dev)
{
PCIIDEState *d = PCI_IDE(dev);
@ -217,28 +208,7 @@ static void pci_piix_ide_exitfn(PCIDevice *dev)
}
}
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
PCIDevice *dev;
dev = pci_create_simple(bus, devfn, "piix3-ide");
pci_ide_create_devs(dev, hd_table);
return dev;
}
/* hd_table must contain 4 block drivers */
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
PCIDevice *dev;
dev = pci_create_simple(bus, devfn, "piix4-ide");
pci_ide_create_devs(dev, hd_table);
return dev;
}
static void piix3_ide_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@ -266,6 +236,7 @@ static const TypeInfo piix3_ide_xen_info = {
.class_init = piix3_ide_class_init,
};
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
static void piix4_ide_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

21
hw/ide/via.c
View file

@ -113,10 +113,7 @@ static void via_ide_set_irq(void *opaque, int n, int level)
}
level = (d->config[0x70] & 0x80) || (d->config[0x78] & 0x80);
n = pci_get_byte(d->config + PCI_INTERRUPT_LINE);
if (n) {
qemu_set_irq(isa_get_irq(NULL, n), level);
}
qemu_set_irq(isa_get_irq(NULL, 14 + n), level);
}
static void via_ide_reset(DeviceState *dev)
@ -167,9 +164,10 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
uint8_t *pci_conf = dev->config;
int i;
pci_config_set_prog_interface(pci_conf, 0x8f); /* native PCI ATA mode */
pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */
pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
dev->wmask[PCI_INTERRUPT_LINE] = 0xf;
dev->wmask[PCI_INTERRUPT_LINE] = 0;
dev->wmask[PCI_CLASS_PROG] = 5;
memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
&d->bus[0], "via-ide0-data", 8);
@ -190,8 +188,6 @@ static void via_ide_realize(PCIDevice *dev, Error **errp)
bmdma_setup_bar(d);
pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
for (i = 0; i < 2; i++) {
ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
ide_init2(&d->bus[i], qemu_allocate_irq(via_ide_set_irq, d, i));
@ -213,20 +209,13 @@ static void via_ide_exitfn(PCIDevice *dev)
}
}
void via_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
{
PCIDevice *dev;
dev = pci_create_simple(bus, devfn, "via-ide");
pci_ide_create_devs(dev, hd_table);
}
static void via_ide_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
dc->reset = via_ide_reset;
dc->vmsd = &vmstate_ide_pci;
k->realize = via_ide_realize;
k->exit = via_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_VIA;

23
hw/isa/piix4.c
View file

@ -34,7 +34,7 @@
#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@ -240,28 +240,25 @@ static void piix4_register_types(void)
type_init(piix4_register_types)
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
I2CBus **smbus, size_t ide_buses)
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
{
size_t ide_drives = ide_buses * MAX_IDE_DEVS;
DriveInfo **hd;
PCIDevice *pci;
DeviceState *dev;
int devfn = PCI_DEVFN(10, 0);
pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
true, TYPE_PIIX4_PCI_DEVICE);
pci = pci_create_simple_multifunction(pci_bus, devfn, true,
TYPE_PIIX4_PCI_DEVICE);
dev = DEVICE(pci);
if (isa_bus) {
*isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
}
hd = g_new(DriveInfo *, ide_drives);
ide_drive_get(hd, ide_drives);
pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
g_free(hd);
pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
pci_ide_create_devs(pci);
pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
if (smbus) {
*smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
*smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
}

8
hw/mips/mips_fulong2e.c
View file

@ -36,7 +36,7 @@
#include "audio/audio.h"
#include "qemu/log.h"
#include "hw/loader.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "elf.h"
#include "hw/isa/vt82c686.h"
#include "hw/rtc/mc146818rtc.h"
@ -238,7 +238,7 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
{
qemu_irq *i8259;
ISABus *isa_bus;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
PCIDevice *dev;
isa_bus = vt82c686b_isa_init(pci_bus, PCI_DEVFN(slot, 0));
if (!isa_bus) {
@ -256,8 +256,8 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
/* Super I/O */
isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
ide_drive_get(hd, ARRAY_SIZE(hd));
via_ide_init(pci_bus, hd, PCI_DEVFN(slot, 1));
dev = pci_create_simple(pci_bus, PCI_DEVFN(slot, 1), "via-ide");
pci_ide_create_devs(dev);
pci_create_simple(pci_bus, PCI_DEVFN(slot, 2), "vt82c686b-usb-uhci");
pci_create_simple(pci_bus, PCI_DEVFN(slot, 3), "vt82c686b-usb-uhci");

2
hw/mips/mips_malta.c
View file

@ -1403,7 +1403,7 @@ void mips_malta_init(MachineState *machine)
pci_bus = gt64120_register(s->i8259);
/* Southbridge */
dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
dev = piix4_create(pci_bus, &isa_bus, &smbus);
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);

1
hw/mips/mips_r4k.c
View file

@ -26,6 +26,7 @@
#include "qemu/log.h"
#include "hw/mips/bios.h"
#include "hw/ide.h"
#include "hw/ide/internal.h"
#include "hw/loader.h"
#include "elf.h"
#include "hw/rtc/mc146818rtc.h"

5
hw/pci/pci.c
View file

@ -302,8 +302,11 @@ static void pci_do_device_reset(PCIDevice *dev)
pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
pci_get_word(dev->wmask + PCI_STATUS) |
pci_get_word(dev->w1cmask + PCI_STATUS));
/* Some devices make bits of PCI_INTERRUPT_LINE read only */
pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE,
pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) |
pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE));
dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
dev->config[PCI_INTERRUPT_LINE] = 0x0;
for (r = 0; r < PCI_NUM_REGIONS; ++r) {
PCIIORegion *region = &dev->io_regions[r];
if (!region->size) {

1
hw/ppc/mac_newworld.c
View file

@ -62,7 +62,6 @@
#include "hw/char/escc.h"
#include "hw/misc/macio/macio.h"
#include "hw/ppc/openpic.h"
#include "hw/ide.h"
#include "hw/loader.h"
#include "hw/fw-path-provider.h"
#include "elf.h"

1
hw/ppc/mac_oldworld.c
View file

@ -41,7 +41,6 @@
#include "hw/nvram/fw_cfg.h"
#include "hw/char/escc.h"
#include "hw/misc/macio/macio.h"
#include "hw/ide.h"
#include "hw/loader.h"
#include "hw/fw-path-provider.h"
#include "elf.h"

1
hw/ppc/prep.c
View file

@ -37,7 +37,6 @@
#include "hw/boards.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "hw/ide.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/rtc/mc146818rtc.h"

6
hw/sparc64/sun4u.c
View file

@ -50,7 +50,6 @@
#include "hw/sparc/sparc64.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/sysbus.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/loader.h"
#include "hw/fw-path-provider.h"
@ -563,7 +562,6 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DeviceState *iommu, *dev;
FWCfgState *fw_cfg;
NICInfo *nd;
@ -663,12 +661,10 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
qemu_macaddr_default_if_unset(&macaddr);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
qdev_init_nofail(&pci_dev->qdev);
pci_ide_create_devs(pci_dev, hd);
pci_ide_create_devs(pci_dev);
/* Map NVRAM into I/O (ebus) space */
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);

9
include/hw/ide.h
View file

@ -2,23 +2,14 @@
#define HW_IDE_H
#include "hw/isa/isa.h"
#include "hw/pci/pci.h"
#include "exec/memory.h"
#define MAX_IDE_DEVS 2
/* ide-isa.c */
ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
DriveInfo *hd0, DriveInfo *hd1);
/* ide-pci.c */
void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
int secondary_ide_enabled);
PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux);
void via_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);
/* ide-mmio.c */
void mmio_ide_init_drives(DeviceState *dev, DriveInfo *hd0, DriveInfo *hd1);

2
include/hw/ide/internal.h
View file

@ -27,6 +27,8 @@ typedef struct IDEDMAOps IDEDMAOps;
#define TYPE_IDE_BUS "IDE"
#define IDE_BUS(obj) OBJECT_CHECK(IDEBus, (obj), TYPE_IDE_BUS)
#define MAX_IDE_DEVS 2
/* Bits of HD_STATUS */
#define ERR_STAT 0x01
#define INDEX_STAT 0x02

3
include/hw/ide/pci.h
View file

@ -2,6 +2,7 @@
#define HW_IDE_PCI_H
#include "hw/ide/internal.h"
#include "hw/pci/pci.h"
#define BM_STATUS_DMAING 0x01
#define BM_STATUS_ERROR 0x02
@ -62,7 +63,7 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
extern MemoryRegionOps bmdma_addr_ioport_ops;
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table);
void pci_ide_create_devs(PCIDevice *dev);
extern const VMStateDescription vmstate_ide_pci;
extern const MemoryRegionOps pci_ide_cmd_le_ops;

1
include/hw/misc/macio/macio.h
View file

@ -27,6 +27,7 @@
#define MACIO_H
#include "hw/char/escc.h"
#include "hw/pci/pci.h"
#include "hw/ide/internal.h"
#include "hw/intc/heathrow_pic.h"
#include "hw/misc/macio/cuda.h"

3
include/hw/southbridge/piix.h
View file

@ -68,7 +68,6 @@ extern PCIDevice *piix4_dev;
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
I2CBus **smbus, size_t ide_buses);
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
#endif

6
tests/qtest/hd-geo-test.c
View file

@ -421,7 +421,7 @@ static char *create_qcow2_with_mbr(MBRpartitions mbr, uint64_t sectors)
char *raw_path = strdup(template);
char *qcow2_path = strdup(template);
char cmd[100 + 2 * PATH_MAX];
uint8_t buf[512];
uint8_t buf[512] = {};
int i, ret, fd, offset;
uint64_t qcow2_size = sectors * 512;
uint8_t status, parttype, head, sector, cyl;
@ -457,8 +457,8 @@ static char *create_qcow2_with_mbr(MBRpartitions mbr, uint64_t sectors)
buf[offset + 0x6] = sector;
buf[offset + 0x7] = cyl;
(*(uint32_t *)&buf[offset + 0x8]) = cpu_to_le32(mbr[i].start_sect);
(*(uint32_t *)&buf[offset + 0xc]) = cpu_to_le32(mbr[i].nr_sects);
stl_le_p(&buf[offset + 0x8], mbr[i].start_sect);
stl_le_p(&buf[offset + 0xc], mbr[i].nr_sects);
offset += 0x10;
}