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target/openrisc: Use cpu_unwind_state_data for mfspr
Since we do not plan to exit, use cpu_unwind_state_data and extract exactly the data requested. This is a bug fix, in that we no longer clobber dflag. Consider: l.j L2 // branch l.mfspr r1, ppc // delay L1: boom L2: l.lwa r3, (r4) Here, dflag would be set by cpu_restore_state (because that is the current state of the cpu), but but not cleared by tb_stop on exiting the TB (because DisasContext has recorded the current value as zero). The next TB begins at L2 with dflag incorrectly set. If the load has a tlb miss, then the exception will be delivered as per a delay slot: with DSX set in the status register and PC decremented (delay slots restart by re-executing the branch). This will cause the return from interrupt to go to L1, and boom! Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -199,6 +199,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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target_ulong spr)
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{
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#ifndef CONFIG_USER_ONLY
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uint64_t data[TARGET_INSN_START_WORDS];
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MachineState *ms = MACHINE(qdev_get_machine());
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OpenRISCCPU *cpu = env_archcpu(env);
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CPUState *cs = env_cpu(env);
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@ -232,14 +233,20 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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return env->evbar;
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case TO_SPR(0, 16): /* NPC (equals PC) */
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cpu_restore_state(cs, GETPC(), false);
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if (cpu_unwind_state_data(cs, GETPC(), data)) {
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return data[0];
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}
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return env->pc;
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case TO_SPR(0, 17): /* SR */
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return cpu_get_sr(env);
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case TO_SPR(0, 18): /* PPC */
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cpu_restore_state(cs, GETPC(), false);
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if (cpu_unwind_state_data(cs, GETPC(), data)) {
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if (data[1] & 2) {
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return data[0] - 4;
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}
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}
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return env->ppc;
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case TO_SPR(0, 32): /* EPCR */
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