system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-10-04 02:04:02 +00:00
Code Issues Packages Projects Releases Wiki Activity

RISC-V: Fix a memory leak when realizing a sifive_e

Browse source 
Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(),
where a pair of recently added MemoryRegion instances would not be freed
if there were errors elsewhere in the function.  The fix here is to
simply not use dynamic allocation for these instances: there's always
one of each in SiFiveESoCState, so instead we just include them within
the struct.

Fixes: 30efbf330a ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Palmer Dabbelt 2019-06-14 04:58:41 -07:00
parent 5b7ae1cec9
commit c988de4119
No known key found for this signature in database
GPG key ID: EF4CA1502CCBAB41
2 changed files with 8 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
hw/riscv/sifive_e.c
View file

@ -158,17 +158,15 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
SiFiveESoCState *s = RISCV_E_SOC(dev);
MemoryRegion *sys_mem = get_system_memory();
MemoryRegion *xip_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
object_property_set_bool(OBJECT(&s->cpus), true, "realized",
&error_abort);
/* Mask ROM */
memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom",
memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom",
memmap[SIFIVE_E_MROM].size, &error_fatal);
memory_region_add_subregion(sys_mem,
memmap[SIFIVE_E_MROM].base, mask_rom);
memmap[SIFIVE_E_MROM].base, &s->mask_rom);
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
@ -228,10 +226,11 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
/* Flash memory */
memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip",
memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip",
memmap[SIFIVE_E_XIP].size, &error_fatal);
memory_region_set_readonly(xip_mem, true);
memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem);
memory_region_set_readonly(&s->xip_mem, true);
memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
&s->xip_mem);
}
static void riscv_sifive_e_machine_init(MachineClass *mc)

2
include/hw/riscv/sifive_e.h
View file

@ -33,6 +33,8 @@ typedef struct SiFiveESoCState {
RISCVHartArrayState cpus;
DeviceState *plic;
SIFIVEGPIOState gpio;
MemoryRegion xip_mem;
MemoryRegion mask_rom;
} SiFiveESoCState;
typedef struct SiFiveEState {