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tcg-aarch64: Use adrp in tcg_out_movi
Loading an qemu pointer as an immediate happens often. E.g. - exit_tb $0x7fa8140013 + exit_tb $0x7f81ee0013 ... - : d2800260 mov x0, #0x13 - : f2b50280 movk x0, #0xa814, lsl #16 - : f2c00fe0 movk x0, #0x7f, lsl #32 + : 90ff1000 adrp x0, 0x7f81ee0000 + : 91004c00 add x0, x0, #0x13 Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -294,6 +294,10 @@ typedef enum {
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I3405_MOVZ = 0x52800000,
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I3405_MOVK = 0x72800000,
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/* PC relative addressing instructions. */
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I3406_ADR = 0x10000000,
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I3406_ADRP = 0x90000000,
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/* Add/subtract shifted register instructions (without a shift). */
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I3502_ADD = 0x0b000000,
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I3502_ADDS = 0x2b000000,
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@ -457,6 +461,12 @@ static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext,
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tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd);
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}
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static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn,
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TCGReg rd, int64_t disp)
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{
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tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);
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}
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/* This function is for both 3.5.2 (Add/Subtract shifted register), for
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the rare occasion when we actually want to supply a shift amount. */
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static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
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@ -596,6 +606,19 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
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return;
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}
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/* Look for host pointer values within 4G of the PC. This happens
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often when loading pointers to QEMU's own data structures. */
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if (type == TCG_TYPE_I64) {
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tcg_target_long disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12);
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if (disp == sextract64(disp, 0, 21)) {
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tcg_out_insn(s, 3406, ADRP, rd, disp);
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if (value & 0xfff) {
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tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);
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}
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return;
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}
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}
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/* Would it take fewer insns to begin with MOVN? For the value and its
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inverse, count the number of 16-bit lanes that are 0. */
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for (i = wantinv = imask = 0; i < 64; i += 16) {
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