mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
LoongArch updates:
Store value in SET_FPU_* macros. Fix unused variable Werrors in acpi-build.c Update xml to match upstream gdb. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmLtdTodHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/u3Qf/XON//wiT054wyL3a wCZ7c4A96zA0Zu+S1FSo4CZ81wCUpAF5b76fhIU5GrLuWrs/UzOcn+akS8LNLLcM nQHqbYNQbkTGOj6DwlZfts8Ul/Ki/Yimjh0gBLFGepzYrsahJ4dCVwQR/KZNkMKf xwBn3+yq96DzEmIqjqEQtlet3Wmsow/zDU+RuHbtdrFiSx6MwhLo/e+dHVEEPkEL EBmFNETcmAzIg+oFfifkP1ZHgL/Nt2yjElwFZM2pKLMgANVpHOpCTap03KAO/xTt LzX5nmJ+4MYPyoEchRaNuq5sB5GqicDGuwGPdhu6qOV589duZ64M4dfm9ErTKEFA eE27rA== =fcsy -----END PGP SIGNATURE----- Merge tag 'pull-la-20220805' of https://gitlab.com/rth7680/qemu into staging LoongArch updates: Store value in SET_FPU_* macros. Fix unused variable Werrors in acpi-build.c Update xml to match upstream gdb. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmLtdTodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/u3Qf/XON//wiT054wyL3a # wCZ7c4A96zA0Zu+S1FSo4CZ81wCUpAF5b76fhIU5GrLuWrs/UzOcn+akS8LNLLcM # nQHqbYNQbkTGOj6DwlZfts8Ul/Ki/Yimjh0gBLFGepzYrsahJ4dCVwQR/KZNkMKf # xwBn3+yq96DzEmIqjqEQtlet3Wmsow/zDU+RuHbtdrFiSx6MwhLo/e+dHVEEPkEL # EBmFNETcmAzIg+oFfifkP1ZHgL/Nt2yjElwFZM2pKLMgANVpHOpCTap03KAO/xTt # LzX5nmJ+4MYPyoEchRaNuq5sB5GqicDGuwGPdhu6qOV589duZ64M4dfm9ErTKEFA # eE27rA== # =fcsy # -----END PGP SIGNATURE----- # gpg: Signature made Fri 05 Aug 2022 12:53:30 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-la-20220805' of https://gitlab.com/rth7680/qemu: target/loongarch: Update gdb_set_fpu() and gdb_get_fpu() target/loongarch: Update loongarch-fpu.xml target/loongarch: update loongarch-base64.xml target/loongarch: add gdb_arch_name() target/loongarch: Fix GDB get the wrong pc hw/loongarch: remove acpi-build.c unused variable 'aml_len' target/loongarch: Fix macros SET_FPU_* in cpu.h Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
c669f22f1a
10 changed files with 119 additions and 110 deletions
|
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@ -1,5 +1,5 @@
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TARGET_ARCH=loongarch64
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TARGET_BASE_ARCH=loongarch
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TARGET_SUPPORTS_MTTCG=y
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TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
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TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
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TARGET_NEED_FDT=y
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|
|
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@ -1,5 +1,5 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2021 Free Software Foundation, Inc.
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<!-- Copyright (C) 2022 Free Software Foundation, Inc.
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||||
Copying and distribution of this file, with or without modification,
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||||
are permitted in any medium without royalty provided the copyright
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||||
|
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@ -8,9 +8,9 @@
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.loongarch.base">
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<reg name="r0" bitsize="64" type="uint64" group="general"/>
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<reg name="r1" bitsize="64" type="uint64" group="general"/>
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<reg name="r2" bitsize="64" type="uint64" group="general"/>
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<reg name="r3" bitsize="64" type="uint64" group="general"/>
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<reg name="r1" bitsize="64" type="code_ptr" group="general"/>
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<reg name="r2" bitsize="64" type="data_ptr" group="general"/>
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<reg name="r3" bitsize="64" type="data_ptr" group="general"/>
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<reg name="r4" bitsize="64" type="uint64" group="general"/>
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<reg name="r5" bitsize="64" type="uint64" group="general"/>
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<reg name="r6" bitsize="64" type="uint64" group="general"/>
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@ -29,7 +29,7 @@
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<reg name="r19" bitsize="64" type="uint64" group="general"/>
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<reg name="r20" bitsize="64" type="uint64" group="general"/>
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<reg name="r21" bitsize="64" type="uint64" group="general"/>
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<reg name="r22" bitsize="64" type="uint64" group="general"/>
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<reg name="r22" bitsize="64" type="data_ptr" group="general"/>
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<reg name="r23" bitsize="64" type="uint64" group="general"/>
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<reg name="r24" bitsize="64" type="uint64" group="general"/>
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<reg name="r25" bitsize="64" type="uint64" group="general"/>
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@ -39,6 +39,7 @@
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<reg name="r29" bitsize="64" type="uint64" group="general"/>
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<reg name="r30" bitsize="64" type="uint64" group="general"/>
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<reg name="r31" bitsize="64" type="uint64" group="general"/>
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<reg name="orig_a0" bitsize="64" type="uint64" group="general"/>
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<reg name="pc" bitsize="64" type="code_ptr" group="general"/>
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<reg name="badvaddr" bitsize="64" type="code_ptr" group="general"/>
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<reg name="badv" bitsize="64" type="code_ptr" group="general"/>
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</feature>
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50
gdb-xml/loongarch-fpu.xml
Normal file
50
gdb-xml/loongarch-fpu.xml
Normal file
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@ -0,0 +1,50 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2021 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.loongarch.fpu">
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<union id="fputype">
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<field name="f" type="ieee_single"/>
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<field name="d" type="ieee_double"/>
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</union>
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<reg name="f0" bitsize="64" type="fputype" group="float"/>
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<reg name="f1" bitsize="64" type="fputype" group="float"/>
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<reg name="f2" bitsize="64" type="fputype" group="float"/>
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<reg name="f3" bitsize="64" type="fputype" group="float"/>
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<reg name="f4" bitsize="64" type="fputype" group="float"/>
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<reg name="f5" bitsize="64" type="fputype" group="float"/>
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<reg name="f6" bitsize="64" type="fputype" group="float"/>
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<reg name="f7" bitsize="64" type="fputype" group="float"/>
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<reg name="f8" bitsize="64" type="fputype" group="float"/>
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<reg name="f9" bitsize="64" type="fputype" group="float"/>
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<reg name="f10" bitsize="64" type="fputype" group="float"/>
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<reg name="f11" bitsize="64" type="fputype" group="float"/>
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<reg name="f12" bitsize="64" type="fputype" group="float"/>
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<reg name="f13" bitsize="64" type="fputype" group="float"/>
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<reg name="f14" bitsize="64" type="fputype" group="float"/>
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<reg name="f15" bitsize="64" type="fputype" group="float"/>
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<reg name="f16" bitsize="64" type="fputype" group="float"/>
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<reg name="f17" bitsize="64" type="fputype" group="float"/>
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<reg name="f18" bitsize="64" type="fputype" group="float"/>
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<reg name="f19" bitsize="64" type="fputype" group="float"/>
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<reg name="f20" bitsize="64" type="fputype" group="float"/>
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<reg name="f21" bitsize="64" type="fputype" group="float"/>
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<reg name="f22" bitsize="64" type="fputype" group="float"/>
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<reg name="f23" bitsize="64" type="fputype" group="float"/>
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<reg name="f24" bitsize="64" type="fputype" group="float"/>
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<reg name="f25" bitsize="64" type="fputype" group="float"/>
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<reg name="f26" bitsize="64" type="fputype" group="float"/>
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<reg name="f27" bitsize="64" type="fputype" group="float"/>
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<reg name="f28" bitsize="64" type="fputype" group="float"/>
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<reg name="f29" bitsize="64" type="fputype" group="float"/>
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<reg name="f30" bitsize="64" type="fputype" group="float"/>
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<reg name="f31" bitsize="64" type="fputype" group="float"/>
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<reg name="fcc" bitsize="64" type="uint64" group="float"/>
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<reg name="fcsr" bitsize="32" type="uint32" group="float"/>
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</feature>
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@ -1,57 +0,0 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2021 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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||||
are permitted in any medium without royalty provided the copyright
|
||||
notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.loongarch.fpu">
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<union id="fpu64type">
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<field name="f" type="ieee_single"/>
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<field name="d" type="ieee_double"/>
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</union>
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<reg name="f0" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f1" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f2" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f3" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f4" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f5" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f6" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f7" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f8" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f9" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f10" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f11" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f12" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f13" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f14" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f15" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f16" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f17" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f18" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f19" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f20" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f21" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f22" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f23" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f24" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f25" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f26" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f27" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f28" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f29" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f30" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f31" bitsize="64" type="fpu64type" group="float"/>
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<reg name="fcc0" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc1" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc2" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc3" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc4" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc5" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc6" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc7" bitsize="8" type="uint8" group="float"/>
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<reg name="fcsr" bitsize="32" type="uint32" group="float"/>
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</feature>
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@ -411,9 +411,8 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
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LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
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GArray *table_offsets;
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AcpiFadtData fadt_data;
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unsigned facs, rsdt, fadt, dsdt;
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unsigned facs, rsdt, dsdt;
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uint8_t *u;
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size_t aml_len = 0;
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GArray *tables_blob = tables->table_data;
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init_common_fadt_data(&fadt_data);
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@ -437,21 +436,13 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
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dsdt = tables_blob->len;
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build_dsdt(tables_blob, tables->linker, machine);
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/*
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* Count the size of the DSDT, we will need it for
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* legacy sizing of ACPI tables.
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*/
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aml_len += tables_blob->len - dsdt;
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/* ACPI tables pointed to by RSDT */
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fadt = tables_blob->len;
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acpi_add_table(table_offsets, tables_blob);
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fadt_data.facs_tbl_offset = &facs;
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fadt_data.dsdt_tbl_offset = &dsdt;
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fadt_data.xdsdt_tbl_offset = &dsdt;
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build_fadt(tables_blob, tables->linker, &fadt_data,
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lams->oem_id, lams->oem_table_id);
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aml_len += tables_blob->len - fadt;
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acpi_add_table(table_offsets, tables_blob);
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build_madt(tables_blob, tables->linker, lams);
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@ -71,26 +71,6 @@ struct extctx_layout {
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struct ctx_layout end;
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};
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/* The kernel's sc_save_fcc macro is a sequence of MOVCF2GR+BSTRINS. */
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static uint64_t read_all_fcc(CPULoongArchState *env)
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{
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uint64_t ret = 0;
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for (int i = 0; i < 8; ++i) {
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ret |= (uint64_t)env->cf[i] << (i * 8);
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}
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return ret;
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}
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/* The kernel's sc_restore_fcc macro is a sequence of BSTRPICK+MOVGR2CF. */
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static void write_all_fcc(CPULoongArchState *env, uint64_t val)
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{
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for (int i = 0; i < 8; ++i) {
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env->cf[i] = (val >> (i * 8)) & 1;
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}
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}
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static abi_ptr extframe_alloc(struct extctx_layout *extctx,
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struct ctx_layout *sctx, unsigned size,
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unsigned align, abi_ptr orig_sp)
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@ -150,7 +130,7 @@ static void setup_sigframe(CPULoongArchState *env,
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for (i = 0; i < 32; ++i) {
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__put_user(env->fpr[i], &fpu_ctx->regs[i]);
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}
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__put_user(read_all_fcc(env), &fpu_ctx->fcc);
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__put_user(read_fcc(env), &fpu_ctx->fcc);
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__put_user(env->fcsr0, &fpu_ctx->fcsr);
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/*
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@ -216,7 +196,7 @@ static void restore_sigframe(CPULoongArchState *env,
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__get_user(env->fpr[i], &fpu_ctx->regs[i]);
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}
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__get_user(fcc, &fpu_ctx->fcc);
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write_all_fcc(env, fcc);
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write_fcc(env, fcc);
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__get_user(env->fcsr0, &fpu_ctx->fcsr);
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restore_fp_status(env);
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}
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|
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@ -661,6 +661,11 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
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};
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#endif
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static gchar *loongarch_gdb_arch_name(CPUState *cs)
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{
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return g_strdup("loongarch64");
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}
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static void loongarch_cpu_class_init(ObjectClass *c, void *data)
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{
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LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
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@ -683,9 +688,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
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cc->gdb_read_register = loongarch_cpu_gdb_read_register;
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cc->gdb_write_register = loongarch_cpu_gdb_write_register;
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cc->disas_set_info = loongarch_cpu_disas_set_info;
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cc->gdb_num_core_regs = 34;
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cc->gdb_num_core_regs = 35;
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cc->gdb_core_xml_file = "loongarch-base64.xml";
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cc->gdb_stop_before_watchpoint = true;
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cc->gdb_arch_name = loongarch_gdb_arch_name;
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|
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#ifdef CONFIG_TCG
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cc->tcg_ops = &loongarch_tcg_ops;
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|
|
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|
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@ -47,11 +47,23 @@ FIELD(FCSR0, FLAGS, 16, 5)
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FIELD(FCSR0, CAUSE, 24, 5)
|
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|
||||
#define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR0, CAUSE)
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||||
#define SET_FP_CAUSE(REG, V) FIELD_DP32(REG, FCSR0, CAUSE, V)
|
||||
#define SET_FP_CAUSE(REG, V) \
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||||
do { \
|
||||
(REG) = FIELD_DP32(REG, FCSR0, CAUSE, V); \
|
||||
} while (0)
|
||||
|
||||
#define GET_FP_ENABLES(REG) FIELD_EX32(REG, FCSR0, ENABLES)
|
||||
#define SET_FP_ENABLES(REG, V) FIELD_DP32(REG, FCSR0, ENABLES, V)
|
||||
#define SET_FP_ENABLES(REG, V) \
|
||||
do { \
|
||||
(REG) = FIELD_DP32(REG, FCSR0, ENABLES, V); \
|
||||
} while (0)
|
||||
|
||||
#define GET_FP_FLAGS(REG) FIELD_EX32(REG, FCSR0, FLAGS)
|
||||
#define SET_FP_FLAGS(REG, V) FIELD_DP32(REG, FCSR0, FLAGS, V)
|
||||
#define SET_FP_FLAGS(REG, V) \
|
||||
do { \
|
||||
(REG) = FIELD_DP32(REG, FCSR0, FLAGS, V); \
|
||||
} while (0)
|
||||
|
||||
#define UPDATE_FP_FLAGS(REG, V) \
|
||||
do { \
|
||||
(REG) |= FIELD_DP32(0, FCSR0, FLAGS, V); \
|
||||
|
|
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|||
|
|
@ -11,6 +11,24 @@
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|||
#include "internals.h"
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#include "exec/gdbstub.h"
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||||
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uint64_t read_fcc(CPULoongArchState *env)
|
||||
{
|
||||
uint64_t ret = 0;
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||||
|
||||
for (int i = 0; i < 8; ++i) {
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ret |= (uint64_t)env->cf[i] << (i * 8);
|
||||
}
|
||||
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return ret;
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||||
}
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||||
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||||
void write_fcc(CPULoongArchState *env, uint64_t val)
|
||||
{
|
||||
for (int i = 0; i < 8; ++i) {
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||||
env->cf[i] = (val >> (i * 8)) & 1;
|
||||
}
|
||||
}
|
||||
|
||||
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
|
||||
{
|
||||
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
|
||||
|
|
@ -19,8 +37,11 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
|
|||
if (0 <= n && n < 32) {
|
||||
return gdb_get_regl(mem_buf, env->gpr[n]);
|
||||
} else if (n == 32) {
|
||||
return gdb_get_regl(mem_buf, env->pc);
|
||||
/* orig_a0 */
|
||||
return gdb_get_regl(mem_buf, 0);
|
||||
} else if (n == 33) {
|
||||
return gdb_get_regl(mem_buf, env->pc);
|
||||
} else if (n == 34) {
|
||||
return gdb_get_regl(mem_buf, env->CSR_BADV);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -36,7 +57,7 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
|
|||
if (0 <= n && n < 32) {
|
||||
env->gpr[n] = tmp;
|
||||
length = sizeof(target_ulong);
|
||||
} else if (n == 32) {
|
||||
} else if (n == 33) {
|
||||
env->pc = tmp;
|
||||
length = sizeof(target_ulong);
|
||||
}
|
||||
|
|
@ -48,9 +69,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env,
|
|||
{
|
||||
if (0 <= n && n < 32) {
|
||||
return gdb_get_reg64(mem_buf, env->fpr[n]);
|
||||
} else if (32 <= n && n < 40) {
|
||||
return gdb_get_reg8(mem_buf, env->cf[n - 32]);
|
||||
} else if (n == 40) {
|
||||
} else if (n == 32) {
|
||||
uint64_t val = read_fcc(env);
|
||||
return gdb_get_reg64(mem_buf, val);
|
||||
} else if (n == 33) {
|
||||
return gdb_get_reg32(mem_buf, env->fcsr0);
|
||||
}
|
||||
return 0;
|
||||
|
|
@ -64,10 +86,11 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
|
|||
if (0 <= n && n < 32) {
|
||||
env->fpr[n] = ldq_p(mem_buf);
|
||||
length = 8;
|
||||
} else if (32 <= n && n < 40) {
|
||||
env->cf[n - 32] = ldub_p(mem_buf);
|
||||
length = 1;
|
||||
} else if (n == 40) {
|
||||
} else if (n == 32) {
|
||||
uint64_t val = ldq_p(mem_buf);
|
||||
write_fcc(env, val);
|
||||
length = 8;
|
||||
} else if (n == 33) {
|
||||
env->fcsr0 = ldl_p(mem_buf);
|
||||
length = 4;
|
||||
}
|
||||
|
|
@ -77,5 +100,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env,
|
|||
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
|
||||
{
|
||||
gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
|
||||
41, "loongarch-fpu64.xml", 0);
|
||||
41, "loongarch-fpu.xml", 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,6 +51,9 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
|||
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
uint64_t read_fcc(CPULoongArchState *env);
|
||||
void write_fcc(CPULoongArchState *env, uint64_t val);
|
||||
|
||||
int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
|
||||
int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
|
||||
void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
|
||||
|
|
|
|||
Loading…
Reference in a new issue