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tcg: get rid of DEF2 in tcg-opc.h
Now that tcg-opc.h is only used in TCG code, get rid of DEF2 in tcg-opc.h. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno
parent
239fda311a
commit
c61aaf7a38
3 changed files with 149 additions and 150 deletions
293
tcg/tcg-opc.h
293
tcg/tcg-opc.h
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@ -21,283 +21,284 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef DEF2
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#define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs)
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#endif
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/*
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* DEF(name, oargs, iargs, cargs, flags)
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*/
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/* predefined ops */
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DEF2(end, 0, 0, 0, 0) /* must be kept first */
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DEF2(nop, 0, 0, 0, 0)
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DEF2(nop1, 0, 0, 1, 0)
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DEF2(nop2, 0, 0, 2, 0)
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DEF2(nop3, 0, 0, 3, 0)
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DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */
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DEF(end, 0, 0, 0, 0) /* must be kept first */
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DEF(nop, 0, 0, 0, 0)
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DEF(nop1, 0, 0, 1, 0)
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DEF(nop2, 0, 0, 2, 0)
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DEF(nop3, 0, 0, 3, 0)
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DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
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DEF2(discard, 1, 0, 0, 0)
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DEF(discard, 1, 0, 0, 0)
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DEF2(set_label, 0, 0, 1, 0)
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DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
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DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(set_label, 0, 0, 1, 0)
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DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
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DEF(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF2(mov_i32, 1, 1, 0, 0)
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DEF2(movi_i32, 1, 0, 1, 0)
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DEF2(setcond_i32, 1, 2, 1, 0)
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DEF(mov_i32, 1, 1, 0, 0)
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DEF(movi_i32, 1, 0, 1, 0)
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DEF(setcond_i32, 1, 2, 1, 0)
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/* load/store */
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DEF2(ld8u_i32, 1, 1, 1, 0)
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DEF2(ld8s_i32, 1, 1, 1, 0)
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DEF2(ld16u_i32, 1, 1, 1, 0)
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DEF2(ld16s_i32, 1, 1, 1, 0)
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DEF2(ld_i32, 1, 1, 1, 0)
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DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(ld8u_i32, 1, 1, 1, 0)
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DEF(ld8s_i32, 1, 1, 1, 0)
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DEF(ld16u_i32, 1, 1, 1, 0)
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DEF(ld16s_i32, 1, 1, 1, 0)
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DEF(ld_i32, 1, 1, 1, 0)
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DEF(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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/* arith */
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DEF2(add_i32, 1, 2, 0, 0)
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DEF2(sub_i32, 1, 2, 0, 0)
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DEF2(mul_i32, 1, 2, 0, 0)
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DEF(add_i32, 1, 2, 0, 0)
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DEF(sub_i32, 1, 2, 0, 0)
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DEF(mul_i32, 1, 2, 0, 0)
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#ifdef TCG_TARGET_HAS_div_i32
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DEF2(div_i32, 1, 2, 0, 0)
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DEF2(divu_i32, 1, 2, 0, 0)
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DEF2(rem_i32, 1, 2, 0, 0)
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DEF2(remu_i32, 1, 2, 0, 0)
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DEF(div_i32, 1, 2, 0, 0)
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DEF(divu_i32, 1, 2, 0, 0)
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DEF(rem_i32, 1, 2, 0, 0)
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DEF(remu_i32, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_div2_i32
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DEF2(div2_i32, 2, 3, 0, 0)
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DEF2(divu2_i32, 2, 3, 0, 0)
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DEF(div2_i32, 2, 3, 0, 0)
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DEF(divu2_i32, 2, 3, 0, 0)
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#endif
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DEF2(and_i32, 1, 2, 0, 0)
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DEF2(or_i32, 1, 2, 0, 0)
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DEF2(xor_i32, 1, 2, 0, 0)
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DEF(and_i32, 1, 2, 0, 0)
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DEF(or_i32, 1, 2, 0, 0)
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DEF(xor_i32, 1, 2, 0, 0)
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/* shifts/rotates */
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DEF2(shl_i32, 1, 2, 0, 0)
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DEF2(shr_i32, 1, 2, 0, 0)
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DEF2(sar_i32, 1, 2, 0, 0)
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DEF(shl_i32, 1, 2, 0, 0)
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DEF(shr_i32, 1, 2, 0, 0)
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DEF(sar_i32, 1, 2, 0, 0)
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#ifdef TCG_TARGET_HAS_rot_i32
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DEF2(rotl_i32, 1, 2, 0, 0)
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DEF2(rotr_i32, 1, 2, 0, 0)
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DEF(rotl_i32, 1, 2, 0, 0)
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DEF(rotr_i32, 1, 2, 0, 0)
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#endif
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DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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#if TCG_TARGET_REG_BITS == 32
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DEF2(add2_i32, 2, 4, 0, 0)
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DEF2(sub2_i32, 2, 4, 0, 0)
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DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF2(mulu2_i32, 2, 2, 0, 0)
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DEF2(setcond2_i32, 1, 4, 1, 0)
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DEF(add2_i32, 2, 4, 0, 0)
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DEF(sub2_i32, 2, 4, 0, 0)
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DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(mulu2_i32, 2, 2, 0, 0)
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DEF(setcond2_i32, 1, 4, 1, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext8s_i32
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DEF2(ext8s_i32, 1, 1, 0, 0)
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DEF(ext8s_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext16s_i32
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DEF2(ext16s_i32, 1, 1, 0, 0)
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DEF(ext16s_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext8u_i32
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DEF2(ext8u_i32, 1, 1, 0, 0)
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DEF(ext8u_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext16u_i32
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DEF2(ext16u_i32, 1, 1, 0, 0)
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DEF(ext16u_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_bswap16_i32
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DEF2(bswap16_i32, 1, 1, 0, 0)
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DEF(bswap16_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_bswap32_i32
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DEF2(bswap32_i32, 1, 1, 0, 0)
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DEF(bswap32_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_not_i32
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DEF2(not_i32, 1, 1, 0, 0)
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DEF(not_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_neg_i32
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DEF2(neg_i32, 1, 1, 0, 0)
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DEF(neg_i32, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_andc_i32
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DEF2(andc_i32, 1, 2, 0, 0)
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DEF(andc_i32, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_orc_i32
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DEF2(orc_i32, 1, 2, 0, 0)
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DEF(orc_i32, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_eqv_i32
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DEF2(eqv_i32, 1, 2, 0, 0)
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DEF(eqv_i32, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_nand_i32
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DEF2(nand_i32, 1, 2, 0, 0)
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DEF(nand_i32, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_nor_i32
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DEF2(nor_i32, 1, 2, 0, 0)
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DEF(nor_i32, 1, 2, 0, 0)
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#endif
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#if TCG_TARGET_REG_BITS == 64
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DEF2(mov_i64, 1, 1, 0, 0)
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DEF2(movi_i64, 1, 0, 1, 0)
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DEF2(setcond_i64, 1, 2, 1, 0)
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DEF(mov_i64, 1, 1, 0, 0)
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DEF(movi_i64, 1, 0, 1, 0)
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DEF(setcond_i64, 1, 2, 1, 0)
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/* load/store */
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DEF2(ld8u_i64, 1, 1, 1, 0)
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DEF2(ld8s_i64, 1, 1, 1, 0)
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DEF2(ld16u_i64, 1, 1, 1, 0)
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DEF2(ld16s_i64, 1, 1, 1, 0)
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DEF2(ld32u_i64, 1, 1, 1, 0)
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DEF2(ld32s_i64, 1, 1, 1, 0)
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DEF2(ld_i64, 1, 1, 1, 0)
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DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(ld8u_i64, 1, 1, 1, 0)
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DEF(ld8s_i64, 1, 1, 1, 0)
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DEF(ld16u_i64, 1, 1, 1, 0)
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DEF(ld16s_i64, 1, 1, 1, 0)
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DEF(ld32u_i64, 1, 1, 1, 0)
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DEF(ld32s_i64, 1, 1, 1, 0)
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DEF(ld_i64, 1, 1, 1, 0)
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DEF(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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DEF(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
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/* arith */
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DEF2(add_i64, 1, 2, 0, 0)
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DEF2(sub_i64, 1, 2, 0, 0)
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DEF2(mul_i64, 1, 2, 0, 0)
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DEF(add_i64, 1, 2, 0, 0)
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DEF(sub_i64, 1, 2, 0, 0)
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DEF(mul_i64, 1, 2, 0, 0)
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#ifdef TCG_TARGET_HAS_div_i64
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DEF2(div_i64, 1, 2, 0, 0)
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DEF2(divu_i64, 1, 2, 0, 0)
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DEF2(rem_i64, 1, 2, 0, 0)
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DEF2(remu_i64, 1, 2, 0, 0)
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DEF(div_i64, 1, 2, 0, 0)
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DEF(divu_i64, 1, 2, 0, 0)
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DEF(rem_i64, 1, 2, 0, 0)
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DEF(remu_i64, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_div2_i64
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DEF2(div2_i64, 2, 3, 0, 0)
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DEF2(divu2_i64, 2, 3, 0, 0)
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DEF(div2_i64, 2, 3, 0, 0)
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DEF(divu2_i64, 2, 3, 0, 0)
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#endif
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DEF2(and_i64, 1, 2, 0, 0)
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DEF2(or_i64, 1, 2, 0, 0)
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DEF2(xor_i64, 1, 2, 0, 0)
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DEF(and_i64, 1, 2, 0, 0)
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DEF(or_i64, 1, 2, 0, 0)
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DEF(xor_i64, 1, 2, 0, 0)
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/* shifts/rotates */
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DEF2(shl_i64, 1, 2, 0, 0)
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DEF2(shr_i64, 1, 2, 0, 0)
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DEF2(sar_i64, 1, 2, 0, 0)
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DEF(shl_i64, 1, 2, 0, 0)
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DEF(shr_i64, 1, 2, 0, 0)
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DEF(sar_i64, 1, 2, 0, 0)
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#ifdef TCG_TARGET_HAS_rot_i64
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DEF2(rotl_i64, 1, 2, 0, 0)
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DEF2(rotr_i64, 1, 2, 0, 0)
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DEF(rotl_i64, 1, 2, 0, 0)
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DEF(rotr_i64, 1, 2, 0, 0)
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#endif
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DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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#ifdef TCG_TARGET_HAS_ext8s_i64
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DEF2(ext8s_i64, 1, 1, 0, 0)
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DEF(ext8s_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext16s_i64
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DEF2(ext16s_i64, 1, 1, 0, 0)
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DEF(ext16s_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext32s_i64
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DEF2(ext32s_i64, 1, 1, 0, 0)
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DEF(ext32s_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext8u_i64
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DEF2(ext8u_i64, 1, 1, 0, 0)
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DEF(ext8u_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext16u_i64
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DEF2(ext16u_i64, 1, 1, 0, 0)
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DEF(ext16u_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_ext32u_i64
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DEF2(ext32u_i64, 1, 1, 0, 0)
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DEF(ext32u_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_bswap16_i64
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DEF2(bswap16_i64, 1, 1, 0, 0)
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DEF(bswap16_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_bswap32_i64
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DEF2(bswap32_i64, 1, 1, 0, 0)
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DEF(bswap32_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_bswap64_i64
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DEF2(bswap64_i64, 1, 1, 0, 0)
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DEF(bswap64_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_not_i64
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DEF2(not_i64, 1, 1, 0, 0)
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DEF(not_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_neg_i64
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DEF2(neg_i64, 1, 1, 0, 0)
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DEF(neg_i64, 1, 1, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_andc_i64
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DEF2(andc_i64, 1, 2, 0, 0)
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DEF(andc_i64, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_orc_i64
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DEF2(orc_i64, 1, 2, 0, 0)
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DEF(orc_i64, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_eqv_i64
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DEF2(eqv_i64, 1, 2, 0, 0)
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DEF(eqv_i64, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_nand_i64
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DEF2(nand_i64, 1, 2, 0, 0)
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DEF(nand_i64, 1, 2, 0, 0)
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#endif
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#ifdef TCG_TARGET_HAS_nor_i64
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DEF2(nor_i64, 1, 2, 0, 0)
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DEF(nor_i64, 1, 2, 0, 0)
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#endif
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#endif
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/* QEMU specific */
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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DEF2(debug_insn_start, 0, 0, 2, 0)
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DEF(debug_insn_start, 0, 0, 2, 0)
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#else
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DEF2(debug_insn_start, 0, 0, 1, 0)
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DEF(debug_insn_start, 0, 0, 1, 0)
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#endif
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DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
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/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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constants must be defined */
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#if TCG_TARGET_REG_BITS == 32
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#if TARGET_LONG_BITS == 32
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DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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#else
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DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld32, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
#if TARGET_LONG_BITS == 32
|
||||
DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#else
|
||||
DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
#endif
|
||||
|
||||
#else /* TCG_TARGET_REG_BITS == 32 */
|
||||
|
||||
DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld32, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
|
||||
DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
|
||||
#endif /* TCG_TARGET_REG_BITS != 32 */
|
||||
|
||||
#undef DEF2
|
||||
#undef DEF
|
||||
|
|
|
|||
|
|
@ -69,11 +69,9 @@ static void patch_reloc(uint8_t *code_ptr, int type,
|
|||
tcg_target_long value, tcg_target_long addend);
|
||||
|
||||
static TCGOpDef tcg_op_defs[] = {
|
||||
#define DEF(s, n) { #s, 0, 0, n, n, 0 },
|
||||
#define DEF2(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags, 0 },
|
||||
#define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags, 0 },
|
||||
#include "tcg-opc.h"
|
||||
#undef DEF
|
||||
#undef DEF2
|
||||
};
|
||||
|
||||
static TCGRegSet tcg_target_available_regs[2];
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ typedef uint64_t TCGRegSet;
|
|||
#endif
|
||||
|
||||
typedef enum TCGOpcode {
|
||||
#define DEF(s, n) INDEX_op_ ## s,
|
||||
#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
|
||||
#include "tcg-opc.h"
|
||||
#undef DEF
|
||||
NB_OPS,
|
||||
|
|
|
|||
Loading…
Reference in a new issue