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target/riscv: rvv-1.0: floating-point move instruction

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NaN-boxed the scalar floating-point register based on RVV 1.0's rules.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-38-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2021-12-10 15:56:23 +08:00 committed by Alistair Francis
parent dedc53cbc9
commit c4b3e46f00
1 changed files with 14 additions and 2 deletions
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16
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2461,9 +2461,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
TCGv_i64 t1;
if (s->vl_eq_vlmax) {
t1 = tcg_temp_new_i64();
/* NaN-box f[rs1] */
do_nanbox(s, t1, cpu_fpr[a->rs1]);
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
MAXSZ(s), MAXSZ(s), t1);
mark_vs_dirty(s);
} else {
TCGv_ptr dest;
@ -2477,15 +2483,21 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
t1 = tcg_temp_new_i64();
/* NaN-box f[rs1] */
do_nanbox(s, t1, cpu_fpr[a->rs1]);
dest = tcg_temp_new_ptr();
desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
fns[s->sew - 1](dest, t1, cpu_env, desc);
tcg_temp_free_ptr(dest);
mark_vs_dirty(s);
gen_set_label(over);
}
tcg_temp_free_i64(t1);
return true;
}
return false;