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https://gitlab.com/qemu-project/qemu
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vmxcap: port to Python 3
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
parent
cf0f7cf903
commit
c3e31eaa21
1 changed files with 7 additions and 7 deletions
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@ -27,9 +27,9 @@ MSR_IA32_VMX_VMFUNC = 0x491
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class msr(object):
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def __init__(self):
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try:
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self.f = open('/dev/cpu/0/msr', 'r', 0)
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self.f = open('/dev/cpu/0/msr', 'rb', 0)
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except:
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self.f = open('/dev/msr0', 'r', 0)
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self.f = open('/dev/msr0', 'rb', 0)
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def read(self, index, default = None):
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import struct
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self.f.seek(index)
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@ -49,7 +49,7 @@ class Control(object):
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val = m.read(nr, 0)
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return (val & 0xffffffff, val >> 32)
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def show(self):
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print self.name
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print(self.name)
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mbz, mb1 = self.read2(self.cap_msr)
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tmbz, tmb1 = 0, 0
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if self.true_cap_msr:
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@ -69,7 +69,7 @@ class Control(object):
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s = 'forced'
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elif one and zero:
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s = 'yes'
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print ' %-40s %s' % (self.bits[bit], s)
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print(' %-40s %s' % (self.bits[bit], s))
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class Misc(object):
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def __init__(self, name, bits, msr):
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@ -77,9 +77,9 @@ class Misc(object):
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self.bits = bits
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self.msr = msr
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def show(self):
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print self.name
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print(self.name)
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value = msr().read(self.msr, 0)
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print ' Hex: 0x%x' % (value)
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print(' Hex: 0x%x' % (value))
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def first_bit(key):
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if type(key) is tuple:
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return key[0]
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@ -94,7 +94,7 @@ class Misc(object):
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def fmt(x):
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return { True: 'yes', False: 'no' }[x]
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v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
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print ' %-40s %s' % (self.bits[bits], fmt(v))
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print(' %-40s %s' % (self.bits[bits], fmt(v)))
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controls = [
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Misc(
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