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target/arm: Expand vector registers for SVE
Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg. The previous patches have made the change in representation relatively painless. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180123035349.24538-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
4cbca7d9b4
commit
c39c2b9043
4 changed files with 81 additions and 28 deletions
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@ -153,6 +153,42 @@ typedef struct {
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uint32_t base_mask;
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} TCR;
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/* Define a maximum sized vector register.
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* For 32-bit, this is a 128-bit NEON/AdvSIMD register.
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* For 64-bit, this is a 2048-bit SVE register.
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*
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* Note that the mapping between S, D, and Q views of the register bank
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* differs between AArch64 and AArch32.
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* In AArch32:
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* Qn = regs[n].d[1]:regs[n].d[0]
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* Dn = regs[n / 2].d[n & 1]
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* Sn = regs[n / 4].d[n % 4 / 2],
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* bits 31..0 for even n, and bits 63..32 for odd n
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* (and regs[16] to regs[31] are inaccessible)
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* In AArch64:
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* Zn = regs[n].d[*]
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* Qn = regs[n].d[1]:regs[n].d[0]
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* Dn = regs[n].d[0]
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* Sn = regs[n].d[0] bits 31..0
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*
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* This corresponds to the architecturally defined mapping between
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* the two execution states, and means we do not need to explicitly
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* map these registers when changing states.
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*
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* Align the data for use with TCG host vector operations.
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*/
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#ifdef TARGET_AARCH64
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# define ARM_MAX_VQ 16
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#else
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# define ARM_MAX_VQ 1
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#endif
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typedef struct ARMVectorReg {
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uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
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} ARMVectorReg;
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typedef struct CPUARMState {
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/* Regs for current mode. */
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uint32_t regs[16];
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@ -477,22 +513,7 @@ typedef struct CPUARMState {
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/* VFP coprocessor state. */
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struct {
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/* VFP/Neon register state. Note that the mapping between S, D and Q
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* views of the register bank differs between AArch64 and AArch32:
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* In AArch32:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[n]
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* Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
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* (and regs[32] to regs[63] are inaccessible)
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* In AArch64:
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* Qn = regs[2n+1]:regs[2n]
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* Dn = regs[2n]
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* Sn = regs[2n] bits 31..0
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* This corresponds to the architecturally defined mapping between
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* the two execution states, and means we do not need to explicitly
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* map these registers when changing states.
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*/
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uint64_t regs[64] QEMU_ALIGNED(16);
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ARMVectorReg zregs[32];
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uint32_t xregs[16];
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/* We store these fpcsr fields separately for convenience. */
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@ -2799,7 +2820,7 @@ static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
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*/
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static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[regno];
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return &env->vfp.zregs[regno >> 1].d[regno & 1];
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}
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/**
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@ -2808,7 +2829,7 @@ static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
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*/
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static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[2 * regno];
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return &env->vfp.zregs[regno].d[0];
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}
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/**
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@ -2817,7 +2838,7 @@ static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
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*/
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static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
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{
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return &env->vfp.regs[2 * regno];
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return &env->vfp.zregs[regno].d[0];
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}
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#endif
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@ -50,7 +50,40 @@ static const VMStateDescription vmstate_vfp = {
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.minimum_version_id = 3,
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.needed = vfp_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64),
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/* For compatibility, store Qn out of Zn here. */
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2),
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VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2),
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/* The xregs array is a little awkward because element 1 (FPSCR)
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* requires a specific accessor, so we have to split it up in
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* the vmstate:
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@ -525,8 +525,8 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
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{
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int offs = 0;
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#ifdef HOST_WORDS_BIGENDIAN
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/* This is complicated slightly because vfp.regs[2n] is
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* still the low half and vfp.regs[2n+1] the high half
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/* This is complicated slightly because vfp.zregs[n].d[0] is
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* still the low half and vfp.zregs[n].d[1] the high half
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* of the 128 bit vector, even on big endian systems.
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* Calculate the offset assuming a fully bigendian 128 bits,
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* then XOR to account for the order of the two 64 bit halves.
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@ -536,7 +536,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
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#else
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offs += element * (1 << size);
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#endif
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offs += offsetof(CPUARMState, vfp.regs[regno * 2]);
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offs += offsetof(CPUARMState, vfp.zregs[regno]);
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assert_fp_access_checked(s);
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return offs;
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}
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@ -545,7 +545,7 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
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static inline int vec_full_reg_offset(DisasContext *s, int regno)
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{
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assert_fp_access_checked(s);
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return offsetof(CPUARMState, vfp.regs[regno * 2]);
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return offsetof(CPUARMState, vfp.zregs[regno]);
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}
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/* Return a newly allocated pointer to the vector register. */
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@ -1512,13 +1512,12 @@ static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr)
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}
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}
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static inline long
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vfp_reg_offset (int dp, int reg)
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static inline long vfp_reg_offset(bool dp, unsigned reg)
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{
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if (dp) {
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return offsetof(CPUARMState, vfp.regs[reg]);
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return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
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} else {
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long ofs = offsetof(CPUARMState, vfp.regs[reg >> 1]);
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long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]);
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if (reg & 1) {
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ofs += offsetof(CPU_DoubleU, l.upper);
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} else {
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