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target/arm: Implement SVE2 saturating multiply-add long

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-24 18:03:00 -07:00 committed by Peter Maydell
parent e0ae6ec383
commit bfc9307ee1
4 changed files with 112 additions and 0 deletions
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14
target/arm/helper-sve.h
View file

@ -2559,3 +2559,17 @@ DEF_HELPER_FLAGS_5(sve2_bcax, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_bsl1n, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_bsl2n, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_nbsl, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlal_zzzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlal_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlal_zzzw_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlsl_zzzw_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlsl_zzzw_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlsl_zzzw_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)

14
target/arm/sve.decode
View file

@ -1332,3 +1332,17 @@ FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm
FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm
FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm
FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm
#### SVE Integer Multiply-Add (unpredicated)
## SVE2 saturating multiply-add long
SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm
SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm
SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm
SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm
## SVE2 saturating multiply-add interleaved long
SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm
SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm

30
target/arm/sve_helper.c
View file

@ -1405,6 +1405,36 @@ void HELPER(sve2_adcl_d)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
}
}
#define DO_SQDMLAL(NAME, TYPEW, TYPEN, HW, HN, DMUL_OP, SUM_OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
{ \
intptr_t i, opr_sz = simd_oprsz(desc); \
int sel1 = extract32(desc, SIMD_DATA_SHIFT, 1) * sizeof(TYPEN); \
int sel2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(TYPEN); \
for (i = 0; i < opr_sz; i += sizeof(TYPEW)) { \
TYPEW nn = *(TYPEN *)(vn + HN(i + sel1)); \
TYPEW mm = *(TYPEN *)(vm + HN(i + sel2)); \
TYPEW aa = *(TYPEW *)(va + HW(i)); \
*(TYPEW *)(vd + HW(i)) = SUM_OP(aa, DMUL_OP(nn, mm)); \
} \
}
DO_SQDMLAL(sve2_sqdmlal_zzzw_h, int16_t, int8_t, H1_2, H1,
do_sqdmull_h, DO_SQADD_H)
DO_SQDMLAL(sve2_sqdmlal_zzzw_s, int32_t, int16_t, H1_4, H1_2,
do_sqdmull_s, DO_SQADD_S)
DO_SQDMLAL(sve2_sqdmlal_zzzw_d, int64_t, int32_t, , H1_4,
do_sqdmull_d, do_sqadd_d)
DO_SQDMLAL(sve2_sqdmlsl_zzzw_h, int16_t, int8_t, H1_2, H1,
do_sqdmull_h, DO_SQSUB_H)
DO_SQDMLAL(sve2_sqdmlsl_zzzw_s, int32_t, int16_t, H1_4, H1_2,
do_sqdmull_s, DO_SQSUB_S)
DO_SQDMLAL(sve2_sqdmlsl_zzzw_d, int64_t, int32_t, , H1_4,
do_sqdmull_d, do_sqsub_d)
#undef DO_SQDMLAL
#define DO_BITPERM(NAME, TYPE, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \

54
target/arm/translate-sve.c
View file

@ -7508,3 +7508,57 @@ DO_SVE2_ZPZZ_FP(FMAXNMP, fmaxnmp)
DO_SVE2_ZPZZ_FP(FMINNMP, fminnmp)
DO_SVE2_ZPZZ_FP(FMAXP, fmaxp)
DO_SVE2_ZPZZ_FP(FMINP, fminp)
/*
* SVE Integer Multiply-Add (unpredicated)
*/
static bool do_sqdmlal_zzzw(DisasContext *s, arg_rrrr_esz *a,
bool sel1, bool sel2)
{
static gen_helper_gvec_4 * const fns[] = {
NULL, gen_helper_sve2_sqdmlal_zzzw_h,
gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d,
};
return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
}
static bool do_sqdmlsl_zzzw(DisasContext *s, arg_rrrr_esz *a,
bool sel1, bool sel2)
{
static gen_helper_gvec_4 * const fns[] = {
NULL, gen_helper_sve2_sqdmlsl_zzzw_h,
gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d,
};
return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
}
static bool trans_SQDMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_sqdmlal_zzzw(s, a, false, false);
}
static bool trans_SQDMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_sqdmlal_zzzw(s, a, true, true);
}
static bool trans_SQDMLALBT(DisasContext *s, arg_rrrr_esz *a)
{
return do_sqdmlal_zzzw(s, a, false, true);
}
static bool trans_SQDMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_sqdmlsl_zzzw(s, a, false, false);
}
static bool trans_SQDMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
{
return do_sqdmlsl_zzzw(s, a, true, true);
}
static bool trans_SQDMLSLBT(DisasContext *s, arg_rrrr_esz *a)
{
return do_sqdmlsl_zzzw(s, a, false, true);
}