system/qemu
system/qemu
1
0
Fork 0
mirror of https://gitlab.com/qemu-project/qemu synced 2024-09-06 01:43:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

hw/cxl: Fix missing reserved data in CXL Device DVSEC

Browse source 
The r3.1 specification introduced a new 2 byte field, but
to maintain DWORD alignment, a additional 2 reserved bytes
were added. Forgot those in updating the structure definition
but did include them in the size define leading to a buffer
overrun.

Also use the define so that we don't duplicate the value.

Fixes: Coverity ID 1534095 buffer overrun
Fixes: 8700ee15de ("hw/cxl: Standardize all references on CXL r3.1 and minor updates")
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240308143831.6256-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Jonathan Cameron 2024-03-08 14:38:31 +00:00 committed by Michael S. Tsirkin
parent 74e2845c5f
commit bfc2f7a6ca
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
include/hw/cxl/cxl_pci.h
View file

@ -92,8 +92,9 @@ typedef struct CXLDVSECDevice {
uint32_t range2_base_hi;
uint32_t range2_base_lo;
uint16_t cap3;
uint16_t resv;
} QEMU_PACKED CXLDVSECDevice;
QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != 0x3A);
QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != PCIE_CXL_DEVICE_DVSEC_LENGTH);
/*
* CXL r3.1 Section 8.1.5: CXL Extensions DVSEC for Ports