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Add GE IP-Octal 232 IndustryPack emulation
The GE IP-Octal 232 is an IndustryPack module that implements eight RS-232 serial ports, each one of which can be redirected to a character device in the host. Signed-off-by: Alberto Garcia <agarcia@igalia.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Alberto Garcia
Anthony Liguori
parent
9c16fa79bf
commit
be657dea4b
2 changed files with 620 additions and 1 deletions
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@ -107,7 +107,7 @@ common-obj-$(CONFIG_XGMAC) += xgmac.o
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common-obj-$(CONFIG_PCI) += wdt_i6300esb.o
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# IndustryPack
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common-obj-$(CONFIG_IPACK) += tpci200.o ipack.o
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common-obj-$(CONFIG_IPACK) += tpci200.o ipoctal232.o ipack.o
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# PCI network cards
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common-obj-$(CONFIG_NE2000_PCI) += ne2000.o
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619
hw/ipoctal232.c
Normal file
619
hw/ipoctal232.c
Normal file
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@ -0,0 +1,619 @@
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/*
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* QEMU GE IP-Octal 232 IndustryPack emulation
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*
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* Copyright (C) 2012 Igalia, S.L.
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* Author: Alberto Garcia <agarcia@igalia.com>
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*
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* This code is licensed under the GNU GPL v2 or (at your option) any
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* later version.
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*/
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#include "ipack.h"
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#include "qemu/bitops.h"
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#include "char/char.h"
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/* #define DEBUG_IPOCTAL */
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#ifdef DEBUG_IPOCTAL
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#define DPRINTF2(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF2(fmt, ...) do { } while (0)
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#endif
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#define DPRINTF(fmt, ...) DPRINTF2("IP-Octal: " fmt, ## __VA_ARGS__)
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#define RX_FIFO_SIZE 3
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/* The IP-Octal has 8 channels (a-h)
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divided into 4 blocks (A-D) */
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#define N_CHANNELS 8
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#define N_BLOCKS 4
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#define REG_MRa 0x01
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#define REG_MRb 0x11
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#define REG_SRa 0x03
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#define REG_SRb 0x13
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#define REG_CSRa 0x03
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#define REG_CSRb 0x13
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#define REG_CRa 0x05
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#define REG_CRb 0x15
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#define REG_RHRa 0x07
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#define REG_RHRb 0x17
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#define REG_THRa 0x07
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#define REG_THRb 0x17
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#define REG_ACR 0x09
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#define REG_ISR 0x0B
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#define REG_IMR 0x0B
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#define REG_OPCR 0x1B
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#define CR_ENABLE_RX BIT(0)
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#define CR_DISABLE_RX BIT(1)
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#define CR_ENABLE_TX BIT(2)
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#define CR_DISABLE_TX BIT(3)
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#define CR_CMD(cr) ((cr) >> 4)
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#define CR_NO_OP 0
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#define CR_RESET_MR 1
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#define CR_RESET_RX 2
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#define CR_RESET_TX 3
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#define CR_RESET_ERR 4
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#define CR_RESET_BRKINT 5
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#define CR_START_BRK 6
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#define CR_STOP_BRK 7
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#define CR_ASSERT_RTSN 8
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#define CR_NEGATE_RTSN 9
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#define CR_TIMEOUT_ON 10
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#define CR_TIMEOUT_OFF 12
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#define SR_RXRDY BIT(0)
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#define SR_FFULL BIT(1)
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#define SR_TXRDY BIT(2)
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#define SR_TXEMT BIT(3)
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#define SR_OVERRUN BIT(4)
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#define SR_PARITY BIT(5)
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#define SR_FRAMING BIT(6)
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#define SR_BREAK BIT(7)
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#define ISR_TXRDYA BIT(0)
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#define ISR_RXRDYA BIT(1)
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#define ISR_BREAKA BIT(2)
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#define ISR_CNTRDY BIT(3)
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#define ISR_TXRDYB BIT(4)
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#define ISR_RXRDYB BIT(5)
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#define ISR_BREAKB BIT(6)
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#define ISR_MPICHG BIT(7)
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#define ISR_TXRDY(CH) (((CH) & 1) ? BIT(4) : BIT(0))
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#define ISR_RXRDY(CH) (((CH) & 1) ? BIT(5) : BIT(1))
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#define ISR_BREAK(CH) (((CH) & 1) ? BIT(6) : BIT(2))
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typedef struct IPOctalState IPOctalState;
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typedef struct SCC2698Channel SCC2698Channel;
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typedef struct SCC2698Block SCC2698Block;
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struct SCC2698Channel {
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IPOctalState *ipoctal;
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CharDriverState *dev;
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char *devpath;
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bool rx_enabled;
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uint8_t mr[2];
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uint8_t mr_idx;
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uint8_t sr;
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uint8_t rhr[RX_FIFO_SIZE];
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uint8_t rhr_idx;
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uint8_t rx_pending;
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};
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struct SCC2698Block {
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uint8_t imr;
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uint8_t isr;
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};
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struct IPOctalState {
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IPackDevice dev;
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SCC2698Channel ch[N_CHANNELS];
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SCC2698Block blk[N_BLOCKS];
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uint8_t irq_vector;
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};
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#define TYPE_IPOCTAL "ipoctal232"
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#define IPOCTAL(obj) \
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OBJECT_CHECK(IPOctalState, (obj), TYPE_IPOCTAL)
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static const VMStateDescription vmstate_scc2698_channel = {
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.name = "scc2698_channel",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL(rx_enabled, SCC2698Channel),
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VMSTATE_UINT8_ARRAY(mr, SCC2698Channel, 2),
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VMSTATE_UINT8(mr_idx, SCC2698Channel),
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VMSTATE_UINT8(sr, SCC2698Channel),
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VMSTATE_UINT8_ARRAY(rhr, SCC2698Channel, RX_FIFO_SIZE),
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VMSTATE_UINT8(rhr_idx, SCC2698Channel),
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VMSTATE_UINT8(rx_pending, SCC2698Channel),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_scc2698_block = {
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.name = "scc2698_block",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(imr, SCC2698Block),
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VMSTATE_UINT8(isr, SCC2698Block),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_ipoctal = {
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.name = "ipoctal232",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_IPACK_DEVICE(dev, IPOctalState),
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VMSTATE_STRUCT_ARRAY(ch, IPOctalState, N_CHANNELS, 1,
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vmstate_scc2698_channel, SCC2698Channel),
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VMSTATE_STRUCT_ARRAY(blk, IPOctalState, N_BLOCKS, 1,
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vmstate_scc2698_block, SCC2698Block),
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VMSTATE_UINT8(irq_vector, IPOctalState),
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VMSTATE_END_OF_LIST()
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}
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};
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/* data[10] is 0x0C, not 0x0B as the doc says */
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static const uint8_t id_prom_data[] = {
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0x49, 0x50, 0x41, 0x43, 0xF0, 0x22,
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0xA1, 0x00, 0x00, 0x00, 0x0C, 0xCC
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};
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static void update_irq(IPOctalState *dev, unsigned block)
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{
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/* Blocks A and B interrupt on INT0#, C and D on INT1#.
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Thus, to get the status we have to check two blocks. */
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SCC2698Block *blk0 = &dev->blk[block];
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SCC2698Block *blk1 = &dev->blk[block^1];
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unsigned intno = block / 2;
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if ((blk0->isr & blk0->imr) || (blk1->isr & blk1->imr)) {
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qemu_irq_raise(dev->dev.irq[intno]);
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} else {
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qemu_irq_lower(dev->dev.irq[intno]);
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}
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}
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static void write_cr(IPOctalState *dev, unsigned channel, uint8_t val)
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{
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SCC2698Channel *ch = &dev->ch[channel];
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SCC2698Block *blk = &dev->blk[channel / 2];
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DPRINTF("Write CR%c %u: ", channel + 'a', val);
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/* The lower 4 bits are used to enable and disable Tx and Rx */
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if (val & CR_ENABLE_RX) {
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DPRINTF2("Rx on, ");
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ch->rx_enabled = true;
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}
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if (val & CR_DISABLE_RX) {
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DPRINTF2("Rx off, ");
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ch->rx_enabled = false;
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}
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if (val & CR_ENABLE_TX) {
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DPRINTF2("Tx on, ");
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ch->sr |= SR_TXRDY | SR_TXEMT;
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blk->isr |= ISR_TXRDY(channel);
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}
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if (val & CR_DISABLE_TX) {
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DPRINTF2("Tx off, ");
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ch->sr &= ~(SR_TXRDY | SR_TXEMT);
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blk->isr &= ~ISR_TXRDY(channel);
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}
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DPRINTF2("cmd: ");
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/* The rest of the bits implement different commands */
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switch (CR_CMD(val)) {
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case CR_NO_OP:
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DPRINTF2("none");
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break;
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case CR_RESET_MR:
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DPRINTF2("reset MR");
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ch->mr_idx = 0;
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break;
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case CR_RESET_RX:
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DPRINTF2("reset Rx");
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ch->rx_enabled = false;
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ch->rx_pending = 0;
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ch->sr &= ~SR_RXRDY;
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blk->isr &= ~ISR_RXRDY(channel);
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break;
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case CR_RESET_TX:
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DPRINTF2("reset Tx");
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ch->sr &= ~(SR_TXRDY | SR_TXEMT);
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blk->isr &= ~ISR_TXRDY(channel);
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break;
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case CR_RESET_ERR:
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DPRINTF2("reset err");
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ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK);
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break;
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case CR_RESET_BRKINT:
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DPRINTF2("reset brk ch int");
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blk->isr &= ~(ISR_BREAKA | ISR_BREAKB);
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break;
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default:
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DPRINTF2("unsupported 0x%x", CR_CMD(val));
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}
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DPRINTF2("\n");
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}
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static uint16_t io_read(IPackDevice *ip, uint8_t addr)
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{
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IPOctalState *dev = IPOCTAL(ip);
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uint16_t ret = 0;
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/* addr[7:6]: block (A-D)
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addr[7:5]: channel (a-h)
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addr[5:0]: register */
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unsigned block = addr >> 5;
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unsigned channel = addr >> 4;
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/* Big endian, accessed using 8-bit bytes at odd locations */
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unsigned offset = (addr & 0x1F) ^ 1;
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SCC2698Channel *ch = &dev->ch[channel];
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SCC2698Block *blk = &dev->blk[block];
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uint8_t old_isr = blk->isr;
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switch (offset) {
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case REG_MRa:
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case REG_MRb:
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ret = ch->mr[ch->mr_idx];
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DPRINTF("Read MR%u%c: 0x%x\n", ch->mr_idx + 1, channel + 'a', ret);
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ch->mr_idx = 1;
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break;
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case REG_SRa:
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case REG_SRb:
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ret = ch->sr;
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DPRINTF("Read SR%c: 0x%x\n", channel + 'a', ret);
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break;
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case REG_RHRa:
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case REG_RHRb:
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ret = ch->rhr[ch->rhr_idx];
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if (ch->rx_pending > 0) {
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ch->rx_pending--;
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if (ch->rx_pending == 0) {
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ch->sr &= ~SR_RXRDY;
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blk->isr &= ~ISR_RXRDY(channel);
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if (ch->dev) {
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qemu_chr_accept_input(ch->dev);
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}
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} else {
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ch->rhr_idx = (ch->rhr_idx + 1) % RX_FIFO_SIZE;
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}
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if (ch->sr & SR_BREAK) {
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ch->sr &= ~SR_BREAK;
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blk->isr |= ISR_BREAK(channel);
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}
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}
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DPRINTF("Read RHR%c (0x%x)\n", channel + 'a', ret);
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break;
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case REG_ISR:
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ret = blk->isr;
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DPRINTF("Read ISR%c: 0x%x\n", block + 'A', ret);
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break;
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default:
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DPRINTF("Read unknown/unsupported register 0x%02x\n", offset);
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}
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if (old_isr != blk->isr) {
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update_irq(dev, block);
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}
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return ret;
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}
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static void io_write(IPackDevice *ip, uint8_t addr, uint16_t val)
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{
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IPOctalState *dev = IPOCTAL(ip);
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unsigned reg = val & 0xFF;
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/* addr[7:6]: block (A-D)
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addr[7:5]: channel (a-h)
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addr[5:0]: register */
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unsigned block = addr >> 5;
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unsigned channel = addr >> 4;
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/* Big endian, accessed using 8-bit bytes at odd locations */
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unsigned offset = (addr & 0x1F) ^ 1;
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SCC2698Channel *ch = &dev->ch[channel];
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SCC2698Block *blk = &dev->blk[block];
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uint8_t old_isr = blk->isr;
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uint8_t old_imr = blk->imr;
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switch (offset) {
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case REG_MRa:
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case REG_MRb:
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ch->mr[ch->mr_idx] = reg;
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DPRINTF("Write MR%u%c 0x%x\n", ch->mr_idx + 1, channel + 'a', reg);
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ch->mr_idx = 1;
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break;
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/* Not implemented */
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case REG_CSRa:
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case REG_CSRb:
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DPRINTF("Write CSR%c: 0x%x\n", channel + 'a', reg);
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break;
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case REG_CRa:
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case REG_CRb:
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write_cr(dev, channel, reg);
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break;
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case REG_THRa:
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case REG_THRb:
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if (ch->sr & SR_TXRDY) {
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DPRINTF("Write THR%c (0x%x)\n", channel + 'a', reg);
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if (ch->dev) {
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uint8_t thr = reg;
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qemu_chr_fe_write(ch->dev, &thr, 1);
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}
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} else {
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DPRINTF("Write THR%c (0x%x), Tx disabled\n", channel + 'a', reg);
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}
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break;
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/* Not implemented */
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case REG_ACR:
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DPRINTF("Write ACR%c 0x%x\n", block + 'A', val);
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break;
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case REG_IMR:
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DPRINTF("Write IMR%c 0x%x\n", block + 'A', val);
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blk->imr = reg;
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break;
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/* Not implemented */
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case REG_OPCR:
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DPRINTF("Write OPCR%c 0x%x\n", block + 'A', val);
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break;
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default:
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DPRINTF("Write unknown/unsupported register 0x%02x %u\n", offset, val);
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}
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if (old_isr != blk->isr || old_imr != blk->imr) {
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update_irq(dev, block);
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}
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}
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static uint16_t id_read(IPackDevice *ip, uint8_t addr)
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{
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uint16_t ret = 0;
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unsigned pos = addr / 2; /* The ID PROM data is stored every other byte */
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if (pos < ARRAY_SIZE(id_prom_data)) {
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ret = id_prom_data[pos];
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} else {
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DPRINTF("Attempt to read unavailable PROM data at 0x%x\n", addr);
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}
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return ret;
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}
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static void id_write(IPackDevice *ip, uint8_t addr, uint16_t val)
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{
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IPOctalState *dev = IPOCTAL(ip);
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if (addr == 1) {
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DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
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dev->irq_vector = val; /* Undocumented, but the hw works like that */
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} else {
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DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
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}
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}
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static uint16_t int_read(IPackDevice *ip, uint8_t addr)
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{
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IPOctalState *dev = IPOCTAL(ip);
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/* Read address 0 to ACK INT0# and address 2 to ACK INT1# */
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if (addr != 0 && addr != 2) {
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DPRINTF("Attempt to read from 0x%x\n", addr);
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return 0;
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} else {
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/* Update interrupts if necessary */
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update_irq(dev, addr);
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return dev->irq_vector;
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}
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}
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static void int_write(IPackDevice *ip, uint8_t addr, uint16_t val)
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{
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DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
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}
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static uint16_t mem_read16(IPackDevice *ip, uint32_t addr)
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||||
{
|
||||
DPRINTF("Attempt to read from 0x%x\n", addr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mem_write16(IPackDevice *ip, uint32_t addr, uint16_t val)
|
||||
{
|
||||
DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
|
||||
}
|
||||
|
||||
static uint8_t mem_read8(IPackDevice *ip, uint32_t addr)
|
||||
{
|
||||
DPRINTF("Attempt to read from 0x%x\n", addr);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mem_write8(IPackDevice *ip, uint32_t addr, uint8_t val)
|
||||
{
|
||||
IPOctalState *dev = IPOCTAL(ip);
|
||||
if (addr == 1) {
|
||||
DPRINTF("Write IRQ vector: %u\n", (unsigned) val);
|
||||
dev->irq_vector = val;
|
||||
} else {
|
||||
DPRINTF("Attempt to write 0x%x to 0x%x\n", val, addr);
|
||||
}
|
||||
}
|
||||
|
||||
static int hostdev_can_receive(void *opaque)
|
||||
{
|
||||
SCC2698Channel *ch = opaque;
|
||||
int available_bytes = RX_FIFO_SIZE - ch->rx_pending;
|
||||
return ch->rx_enabled ? available_bytes : 0;
|
||||
}
|
||||
|
||||
static void hostdev_receive(void *opaque, const uint8_t *buf, int size)
|
||||
{
|
||||
SCC2698Channel *ch = opaque;
|
||||
IPOctalState *dev = ch->ipoctal;
|
||||
unsigned pos = ch->rhr_idx + ch->rx_pending;
|
||||
int i;
|
||||
|
||||
assert(size + ch->rx_pending <= RX_FIFO_SIZE);
|
||||
|
||||
/* Copy data to the RxFIFO */
|
||||
for (i = 0; i < size; i++) {
|
||||
pos %= RX_FIFO_SIZE;
|
||||
ch->rhr[pos++] = buf[i];
|
||||
}
|
||||
|
||||
ch->rx_pending += size;
|
||||
|
||||
/* If the RxFIFO was empty raise an interrupt */
|
||||
if (!(ch->sr & SR_RXRDY)) {
|
||||
unsigned block, channel = 0;
|
||||
/* Find channel number to update the ISR register */
|
||||
while (&dev->ch[channel] != ch) {
|
||||
channel++;
|
||||
}
|
||||
block = channel / 2;
|
||||
dev->blk[block].isr |= ISR_RXRDY(channel);
|
||||
ch->sr |= SR_RXRDY;
|
||||
update_irq(dev, block);
|
||||
}
|
||||
}
|
||||
|
||||
static void hostdev_event(void *opaque, int event)
|
||||
{
|
||||
SCC2698Channel *ch = opaque;
|
||||
switch (event) {
|
||||
case CHR_EVENT_OPENED:
|
||||
DPRINTF("Device %s opened\n", ch->dev->label);
|
||||
break;
|
||||
case CHR_EVENT_BREAK: {
|
||||
uint8_t zero = 0;
|
||||
DPRINTF("Device %s received break\n", ch->dev->label);
|
||||
|
||||
if (!(ch->sr & SR_BREAK)) {
|
||||
IPOctalState *dev = ch->ipoctal;
|
||||
unsigned block, channel = 0;
|
||||
|
||||
while (&dev->ch[channel] != ch) {
|
||||
channel++;
|
||||
}
|
||||
block = channel / 2;
|
||||
|
||||
ch->sr |= SR_BREAK;
|
||||
dev->blk[block].isr |= ISR_BREAK(channel);
|
||||
}
|
||||
|
||||
/* Put a zero character in the buffer */
|
||||
hostdev_receive(ch, &zero, 1);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DPRINTF("Device %s received event %d\n", ch->dev->label, event);
|
||||
}
|
||||
}
|
||||
|
||||
static int ipoctal_init(IPackDevice *ip)
|
||||
{
|
||||
IPOctalState *s = IPOCTAL(ip);
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < N_CHANNELS; i++) {
|
||||
SCC2698Channel *ch = &s->ch[i];
|
||||
ch->ipoctal = s;
|
||||
|
||||
/* Redirect IP-Octal channels to host character devices */
|
||||
if (ch->devpath) {
|
||||
const char chr_name[] = "ipoctal";
|
||||
char label[ARRAY_SIZE(chr_name) + 2];
|
||||
static int index;
|
||||
|
||||
snprintf(label, sizeof(label), "%s%d", chr_name, index);
|
||||
|
||||
ch->dev = qemu_chr_new(label, ch->devpath, NULL);
|
||||
|
||||
if (ch->dev) {
|
||||
index++;
|
||||
qemu_chr_add_handlers(ch->dev, hostdev_can_receive,
|
||||
hostdev_receive, hostdev_event, ch);
|
||||
DPRINTF("Redirecting channel %u to %s (%s)\n",
|
||||
i, ch->devpath, label);
|
||||
} else {
|
||||
DPRINTF("Could not redirect channel %u to %s\n",
|
||||
i, ch->devpath);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static Property ipoctal_properties[] = {
|
||||
DEFINE_PROP_STRING("serial0", IPOctalState, ch[0].devpath),
|
||||
DEFINE_PROP_STRING("serial1", IPOctalState, ch[1].devpath),
|
||||
DEFINE_PROP_STRING("serial2", IPOctalState, ch[2].devpath),
|
||||
DEFINE_PROP_STRING("serial3", IPOctalState, ch[3].devpath),
|
||||
DEFINE_PROP_STRING("serial4", IPOctalState, ch[4].devpath),
|
||||
DEFINE_PROP_STRING("serial5", IPOctalState, ch[5].devpath),
|
||||
DEFINE_PROP_STRING("serial6", IPOctalState, ch[6].devpath),
|
||||
DEFINE_PROP_STRING("serial7", IPOctalState, ch[7].devpath),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void ipoctal_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
IPackDeviceClass *ic = IPACK_DEVICE_CLASS(klass);
|
||||
|
||||
ic->init = ipoctal_init;
|
||||
ic->io_read = io_read;
|
||||
ic->io_write = io_write;
|
||||
ic->id_read = id_read;
|
||||
ic->id_write = id_write;
|
||||
ic->int_read = int_read;
|
||||
ic->int_write = int_write;
|
||||
ic->mem_read16 = mem_read16;
|
||||
ic->mem_write16 = mem_write16;
|
||||
ic->mem_read8 = mem_read8;
|
||||
ic->mem_write8 = mem_write8;
|
||||
|
||||
dc->desc = "GE IP-Octal 232 8-channel RS-232 IndustryPack";
|
||||
dc->props = ipoctal_properties;
|
||||
dc->vmsd = &vmstate_ipoctal;
|
||||
}
|
||||
|
||||
static const TypeInfo ipoctal_info = {
|
||||
.name = TYPE_IPOCTAL,
|
||||
.parent = TYPE_IPACK_DEVICE,
|
||||
.instance_size = sizeof(IPOctalState),
|
||||
.class_init = ipoctal_class_init,
|
||||
};
|
||||
|
||||
static void ipoctal_register_types(void)
|
||||
{
|
||||
type_register_static(&ipoctal_info);
|
||||
}
|
||||
|
||||
type_init(ipoctal_register_types)
|
||||
Loading…
Reference in a new issue