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target-mips: Misaligned memory accesses for R6
Release 6 requires misaligned memory access support for all ordinary memory access instructions (for example, LW/SW, LWC1/SWC1). However misaligned support is not provided for certain special memory accesses such as atomics (for example, LL/SC). Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
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@ -1414,6 +1414,7 @@ typedef struct DisasContext {
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int32_t CP0_Config1;
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/* Routine used to access memory */
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int mem_idx;
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TCGMemOp default_tcg_memop_mask;
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uint32_t hflags, saved_hflags;
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int bstate;
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target_ulong btarget;
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@ -2086,12 +2087,14 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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switch (opc) {
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#if defined(TARGET_MIPS64)
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case OPC_LWU:
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(t0, rt);
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opn = "lwu";
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break;
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case OPC_LD:
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(t0, rt);
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opn = "ld";
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break;
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@ -2162,17 +2165,20 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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opn = "lwpc";
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break;
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case OPC_LW:
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(t0, rt);
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opn = "lw";
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break;
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case OPC_LH:
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(t0, rt);
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opn = "lh";
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break;
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case OPC_LHU:
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW);
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tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW |
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ctx->default_tcg_memop_mask);
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gen_store_gpr(t0, rt);
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opn = "lhu";
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break;
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@ -2256,7 +2262,8 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
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switch (opc) {
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#if defined(TARGET_MIPS64)
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case OPC_SD:
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ |
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ctx->default_tcg_memop_mask);
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opn = "sd";
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break;
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case OPC_SDL:
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@ -2271,11 +2278,13 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
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break;
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#endif
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case OPC_SW:
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
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ctx->default_tcg_memop_mask);
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opn = "sw";
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break;
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case OPC_SH:
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW);
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
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ctx->default_tcg_memop_mask);
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opn = "sh";
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break;
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case OPC_SB:
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@ -2352,7 +2361,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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case OPC_LWC1:
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{
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TCGv_i32 fp0 = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL);
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tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
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ctx->default_tcg_memop_mask);
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gen_store_fpr32(ctx, fp0, ft);
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tcg_temp_free_i32(fp0);
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}
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@ -2362,7 +2372,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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{
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TCGv_i32 fp0 = tcg_temp_new_i32();
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gen_load_fpr32(ctx, fp0, ft);
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tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
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tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
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ctx->default_tcg_memop_mask);
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tcg_temp_free_i32(fp0);
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}
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opn = "swc1";
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@ -2370,7 +2381,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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case OPC_LDC1:
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{
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TCGv_i64 fp0 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
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ctx->default_tcg_memop_mask);
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gen_store_fpr64(ctx, fp0, ft);
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tcg_temp_free_i64(fp0);
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}
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@ -2380,7 +2392,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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{
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TCGv_i64 fp0 = tcg_temp_new_i64();
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gen_load_fpr64(ctx, fp0, ft);
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tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ);
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tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ |
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ctx->default_tcg_memop_mask);
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tcg_temp_free_i64(fp0);
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}
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opn = "sdc1";
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@ -19149,6 +19162,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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#else
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ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
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#endif
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ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
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MO_UNALN : MO_ALIGN;
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num_insns = 0;
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max_insns = tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0)
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@ -607,7 +607,7 @@ static const mips_def_t mips_defs[] =
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},
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{
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/* A generic CPU supporting MIPS64 Release 6 ISA.
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FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
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FIXME: Support IEEE 754-2008 FP.
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Eventually this should be replaced by a real CPU model. */
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.name = "MIPS64R6-generic",
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.CP0_PRid = 0x00010000,
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