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target/arm: align exposed ID registers with Linux
In CPUID registers exposed to userspace, some registers were missing and some fields were not exposed. This patch aligns exposed ID registers and their fields with what the upstream kernel currently exposes. Specifically, the following new ID registers/fields are exposed to userspace: ID_AA64PFR1_EL1.BT: bits 3-0 ID_AA64PFR1_EL1.MTE: bits 11-8 ID_AA64PFR1_EL1.SME: bits 27-24 ID_AA64ZFR0_EL1.SVEver: bits 3-0 ID_AA64ZFR0_EL1.AES: bits 7-4 ID_AA64ZFR0_EL1.BitPerm: bits 19-16 ID_AA64ZFR0_EL1.BF16: bits 23-20 ID_AA64ZFR0_EL1.SHA3: bits 35-32 ID_AA64ZFR0_EL1.SM4: bits 43-40 ID_AA64ZFR0_EL1.I8MM: bits 47-44 ID_AA64ZFR0_EL1.F32MM: bits 55-52 ID_AA64ZFR0_EL1.F64MM: bits 59-56 ID_AA64SMFR0_EL1.F32F32: bit 32 ID_AA64SMFR0_EL1.B16F32: bit 34 ID_AA64SMFR0_EL1.F16F32: bit 35 ID_AA64SMFR0_EL1.I8I32: bits 39-36 ID_AA64SMFR0_EL1.F64F64: bit 48 ID_AA64SMFR0_EL1.I16I64: bits 55-52 ID_AA64SMFR0_EL1.FA64: bit 63 ID_AA64MMFR0_EL1.ECV: bits 63-60 ID_AA64MMFR1_EL1.AFP: bits 47-44 ID_AA64MMFR2_EL1.AT: bits 35-32 ID_AA64ISAR0_EL1.RNDR: bits 63-60 ID_AA64ISAR1_EL1.FRINTTS: bits 35-32 ID_AA64ISAR1_EL1.BF16: bits 47-44 ID_AA64ISAR1_EL1.DGH: bits 51-48 ID_AA64ISAR1_EL1.I8MM: bits 55-52 ID_AA64ISAR2_EL1.WFxT: bits 3-0 ID_AA64ISAR2_EL1.RPRES: bits 7-4 ID_AA64ISAR2_EL1.GPA3: bits 11-8 ID_AA64ISAR2_EL1.APA3: bits 15-12 The code is also refactored to use symbolic names for ID register fields for better readability and maintainability. The test case in tests/tcg/aarch64/sysregs.c is also updated to match the intended behavior. Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com> Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -8147,31 +8147,89 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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#ifdef CONFIG_USER_ONLY
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static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
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{ .name = "ID_AA64PFR0_EL1",
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.exported_bits = 0x000f000f00ff0000,
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.fixed_bits = 0x0000000000000011 },
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.exported_bits = R_ID_AA64PFR0_FP_MASK |
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R_ID_AA64PFR0_ADVSIMD_MASK |
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R_ID_AA64PFR0_SVE_MASK |
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R_ID_AA64PFR0_DIT_MASK,
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.fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) |
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(0x1u << R_ID_AA64PFR0_EL1_SHIFT) },
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{ .name = "ID_AA64PFR1_EL1",
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.exported_bits = 0x00000000000000f0 },
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.exported_bits = R_ID_AA64PFR1_BT_MASK |
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R_ID_AA64PFR1_SSBS_MASK |
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R_ID_AA64PFR1_MTE_MASK |
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R_ID_AA64PFR1_SME_MASK },
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{ .name = "ID_AA64PFR*_EL1_RESERVED",
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.is_glob = true },
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{ .name = "ID_AA64ZFR0_EL1" },
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.is_glob = true },
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{ .name = "ID_AA64ZFR0_EL1",
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.exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
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R_ID_AA64ZFR0_AES_MASK |
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R_ID_AA64ZFR0_BITPERM_MASK |
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R_ID_AA64ZFR0_BFLOAT16_MASK |
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R_ID_AA64ZFR0_SHA3_MASK |
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R_ID_AA64ZFR0_SM4_MASK |
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R_ID_AA64ZFR0_I8MM_MASK |
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R_ID_AA64ZFR0_F32MM_MASK |
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R_ID_AA64ZFR0_F64MM_MASK },
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{ .name = "ID_AA64SMFR0_EL1",
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.exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
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R_ID_AA64SMFR0_B16F32_MASK |
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R_ID_AA64SMFR0_F16F32_MASK |
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R_ID_AA64SMFR0_I8I32_MASK |
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R_ID_AA64SMFR0_F64F64_MASK |
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R_ID_AA64SMFR0_I16I64_MASK |
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R_ID_AA64SMFR0_FA64_MASK },
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{ .name = "ID_AA64MMFR0_EL1",
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.fixed_bits = 0x00000000ff000000 },
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{ .name = "ID_AA64MMFR1_EL1" },
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.exported_bits = R_ID_AA64MMFR0_ECV_MASK,
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.fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
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(0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
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{ .name = "ID_AA64MMFR1_EL1",
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.exported_bits = R_ID_AA64MMFR1_AFP_MASK },
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{ .name = "ID_AA64MMFR2_EL1",
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.exported_bits = R_ID_AA64MMFR2_AT_MASK },
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{ .name = "ID_AA64MMFR*_EL1_RESERVED",
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.is_glob = true },
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.is_glob = true },
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{ .name = "ID_AA64DFR0_EL1",
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.fixed_bits = 0x0000000000000006 },
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{ .name = "ID_AA64DFR1_EL1" },
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.fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
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{ .name = "ID_AA64DFR1_EL1" },
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{ .name = "ID_AA64DFR*_EL1_RESERVED",
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.is_glob = true },
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.is_glob = true },
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{ .name = "ID_AA64AFR*",
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.is_glob = true },
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.is_glob = true },
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{ .name = "ID_AA64ISAR0_EL1",
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.exported_bits = 0x00fffffff0fffff0 },
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.exported_bits = R_ID_AA64ISAR0_AES_MASK |
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R_ID_AA64ISAR0_SHA1_MASK |
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R_ID_AA64ISAR0_SHA2_MASK |
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R_ID_AA64ISAR0_CRC32_MASK |
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R_ID_AA64ISAR0_ATOMIC_MASK |
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R_ID_AA64ISAR0_RDM_MASK |
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R_ID_AA64ISAR0_SHA3_MASK |
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R_ID_AA64ISAR0_SM3_MASK |
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R_ID_AA64ISAR0_SM4_MASK |
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R_ID_AA64ISAR0_DP_MASK |
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R_ID_AA64ISAR0_FHM_MASK |
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R_ID_AA64ISAR0_TS_MASK |
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R_ID_AA64ISAR0_RNDR_MASK },
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{ .name = "ID_AA64ISAR1_EL1",
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.exported_bits = 0x000000f0ffffffff },
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.exported_bits = R_ID_AA64ISAR1_DPB_MASK |
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R_ID_AA64ISAR1_APA_MASK |
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R_ID_AA64ISAR1_API_MASK |
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R_ID_AA64ISAR1_JSCVT_MASK |
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R_ID_AA64ISAR1_FCMA_MASK |
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R_ID_AA64ISAR1_LRCPC_MASK |
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R_ID_AA64ISAR1_GPA_MASK |
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R_ID_AA64ISAR1_GPI_MASK |
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R_ID_AA64ISAR1_FRINTTS_MASK |
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R_ID_AA64ISAR1_SB_MASK |
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R_ID_AA64ISAR1_BF16_MASK |
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R_ID_AA64ISAR1_DGH_MASK |
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R_ID_AA64ISAR1_I8MM_MASK },
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{ .name = "ID_AA64ISAR2_EL1",
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.exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
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R_ID_AA64ISAR2_RPRES_MASK |
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R_ID_AA64ISAR2_GPA3_MASK |
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R_ID_AA64ISAR2_APA3_MASK },
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{ .name = "ID_AA64ISAR*_EL1_RESERVED",
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.is_glob = true },
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.is_glob = true },
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};
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modify_arm_cp_regs(v8_idregs, v8_user_idregs);
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#endif
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@ -8508,8 +8566,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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#ifdef CONFIG_USER_ONLY
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static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
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{ .name = "MIDR_EL1",
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.exported_bits = 0x00000000ffffffff },
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{ .name = "REVIDR_EL1" },
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.exported_bits = R_MIDR_EL1_REVISION_MASK |
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R_MIDR_EL1_PARTNUM_MASK |
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R_MIDR_EL1_ARCHITECTURE_MASK |
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R_MIDR_EL1_VARIANT_MASK |
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R_MIDR_EL1_IMPLEMENTER_MASK },
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{ .name = "REVIDR_EL1" },
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};
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modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
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#endif
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@ -23,7 +23,8 @@ config-cc.mak: Makefile
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$(call cc-option,-march=armv8.1-a+sve2, CROSS_CC_HAS_SVE2); \
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$(call cc-option,-march=armv8.3-a, CROSS_CC_HAS_ARMV8_3); \
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$(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
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$(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE)) 3> config-cc.mak
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$(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
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$(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
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-include config-cc.mak
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# Pauth Tests
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ifneq ($(CROSS_CC_HAS_SVE),)
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# System Registers Tests
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AARCH64_TESTS += sysregs
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ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
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sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
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else
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sysregs: CFLAGS+=-march=armv8.1-a+sve
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endif
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# SVE ioctl test
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AARCH64_TESTS += sve-ioctls
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@ -22,6 +22,13 @@
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#define HWCAP_CPUID (1 << 11)
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#endif
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/*
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* Older assemblers don't recognize newer system register names,
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* but we can still access them by the Sn_n_Cn_Cn_n syntax.
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*/
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#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
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#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
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int failed_bit_count;
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/* Read and print system register `id' value */
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@ -112,18 +119,23 @@ int main(void)
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* minimum valid fields - for the purposes of this check allowed
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* to have non-zero values.
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*/
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get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
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get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
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get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
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get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
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get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
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/* TGran4 & TGran64 as pegged to -1 */
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get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
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get_cpu_reg_check_zero(id_aa64mmfr1_el1);
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get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
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get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
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get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000));
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/* EL1/EL0 reported as AA64 only */
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get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011));
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get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0));
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get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0f00,0fff));
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/* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
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get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
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get_cpu_reg_check_zero(id_aa64dfr1_el1);
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get_cpu_reg_check_zero(id_aa64zfr0_el1);
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get_cpu_reg_check_mask(id_aa64zfr0_el1, _m(0ff0,ff0f,00ff,00ff));
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#ifdef HAS_ARMV9_SME
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get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
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#endif
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get_cpu_reg_check_zero(id_aa64afr0_el1);
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get_cpu_reg_check_zero(id_aa64afr1_el1);
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