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tcg/arm: Fix memory barrier encoding
I found with qemu 2.11.x or newer that I would get an illegal instruction
error running some Intel binaries on my ARM chromebook. On investigation,
I found it was quitting on memory barriers.
qemu instruction:
mb $0x31
was translating as:
0x604050cc: 5bf07ff5 blpl #0x600250a8
After patch it gives:
0x604050cc: f57ff05b dmb ish
In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be
correct based on online docs, but due to some endian-related shenanigans it
had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory
barrier for ARMv6) also should be byte swapped (and this patch does so).
I have not checked for correctness of aarch64's barrier instruction.
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Henry Wertz <hwertz10@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit 3f814b8037
)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
This commit is contained in:
parent
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@ -159,8 +159,8 @@ typedef enum {
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INSN_STRD_IMM = 0x004000f0,
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INSN_STRD_REG = 0x000000f0,
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INSN_DMB_ISH = 0x5bf07ff5,
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INSN_DMB_MCR = 0xba0f07ee,
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INSN_DMB_ISH = 0xf57ff05b,
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INSN_DMB_MCR = 0xee070fba,
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/* Architected nop introduced in v6k. */
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/* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
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