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https://gitlab.com/qemu-project/qemu
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ppc patch queue for 2020-04-07
First pull request for qemu-5.1. This includes: * Removal of all remaining cases where we had CAS triggered reboots * A number of improvements to NMI injection * Support for partition scoped radix translation in softmmu * Some fixes for NVDIMM handling * A handful of other minor fixes -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAl6zlgcACgkQbDjKyiDZ s5LhIQ//YRqYuR9JIcIjcL4qFKqk93RrE8KFoxY4Qri7+o6Zru1ATqpVru4tixpd YN0ntF3oMDV/uveQAG771n5iAX7TgbKiOaqIP/qnL6aUEtG4t3KvPhEIZr9Z3kkW eGL8vzObGlkTHJUdGbUaMrpxJZDLW9MADqTVa1PfDGThk3jKCcMqAInBQwFwNifY lAoHJi0SkF8i7ib6dT1Vp+EPw1SYmnLEFyrQU6+jshvxsb9FGNot0widQeSGCJme uolBiO63gxc4AjAt/5PvtAHe1SY9UGUheHp9hMSGoNrFfrCaMgheE8bOsS3MmPJ0 2kEIW4ZIq+CSqnlNlUciaPWn2X5INkXt+XAZyuTSbGC51yLGGpio5fn5CGdDL3wA +mefdJaYvfv5e5UuM38Lv6D7WyPczh2wIDvCOaJP4Lcr+yv0FOgSQOkd6LtnejqV tFqIAVpI7HeNUDmkt/dWRsje6L5gjfPzhA2c1Qm5r7pac4jQXu4POCFP964KXJ1W Ix7qaVOLVcNfSBbHKu79tRHRZjWDiK0SplrHfO6aSUJ/whJ2raT3O8DL9Rbj1M4/ QDYdMvockuwZRWZeYs1+A0LJ3LcPYVpVRvOjGpZEex8DQZ05+Elys33DMEM9MXpK fOiRu/Op286QxEKAkv/xaMMsJpYZ2k+AJXA+7nOCq0SNj0YvF0c= =INvG -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.1-20200507' into staging ppc patch queue for 2020-04-07 First pull request for qemu-5.1. This includes: * Removal of all remaining cases where we had CAS triggered reboots * A number of improvements to NMI injection * Support for partition scoped radix translation in softmmu * Some fixes for NVDIMM handling * A handful of other minor fixes # gpg: Signature made Thu 07 May 2020 06:00:55 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.1-20200507: target-ppc: fix rlwimi, rlwinm, rlwnm for Clang-9 spapr_nvdimm: Tweak error messages spapr_nvdimm.c: make 'label-size' mandatory target/ppc: Add support for Radix partition-scoped translation target/ppc: Rework ppc_radix64_walk_tree() for partition-scoped translation target/ppc: Extend ppc_radix64_check_prot() with a 'partition_scoped' bool target/ppc: Introduce ppc_radix64_xlate() for Radix tree translation spapr: Don't allow unplug of NVLink2 devices target/ppc: Assert if HV mode is set when running under a pseries machine target/ppc: Introduce a relocation bool in ppc_radix64_handle_mmu_fault() target/ppc: Enforce that the root page directory size must be at least 5 spapr: Drop CAS reboot flag spapr/cas: Separate CAS handling from rebuilding the FDT spapr: Simplify selection of radix/hash during CAS ppc/pnv: Add support for NMI interface ppc/spapr: tweak change system reset helper spapr: Don't check capabilities removed between CAS calls target/ppc: Improve syscall exception logging Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
b894c6ed4a
29
hw/ppc/pnv.c
29
hw/ppc/pnv.c
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@ -27,6 +27,7 @@
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#include "sysemu/runstate.h"
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#include "sysemu/cpus.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/hw_accel.h"
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#include "target/ppc/cpu.h"
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#include "qemu/log.h"
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#include "hw/ppc/fdt.h"
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@ -34,6 +35,7 @@
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_core.h"
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#include "hw/loader.h"
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#include "hw/nmi.h"
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#include "exec/address-spaces.h"
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#include "qapi/visitor.h"
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#include "monitor/monitor.h"
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@ -1977,10 +1979,35 @@ static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
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}
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}
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static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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cpu_synchronize_state(cs);
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ppc_cpu_do_system_reset(cs);
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/*
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* SRR1[42:45] is set to 0100 which the ISA defines as implementation
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* dependent. POWER processors use this for xscom triggered interrupts,
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* which come from the BMC or NMI IPIs.
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*/
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env->spr[SPR_SRR1] |= PPC_BIT(43);
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}
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static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
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{
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CPUState *cs;
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CPU_FOREACH(cs) {
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async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
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}
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}
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static void pnv_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
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NMIClass *nc = NMI_CLASS(oc);
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mc->desc = "IBM PowerNV (Non-Virtualized)";
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mc->init = pnv_init;
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@ -1997,6 +2024,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data)
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mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE;
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mc->default_ram_id = "pnv.ram";
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ispc->print_info = pnv_pic_print_info;
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nc->nmi_monitor_handler = pnv_nmi;
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object_class_property_add_bool(oc, "hb-mode",
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pnv_machine_get_hb, pnv_machine_set_hb,
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@ -2060,6 +2088,7 @@ static const TypeInfo types[] = {
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.class_size = sizeof(PnvMachineClass),
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_INTERRUPT_STATS_PROVIDER },
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{ TYPE_NMI },
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{ },
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},
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},
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@ -96,7 +96,6 @@
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*
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* We load our kernel at 4M, leaving space for SLOF initial image
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*/
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#define FDT_MAX_SIZE 0x100000
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#define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
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#define FW_MAX_SIZE 0x400000
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#define FW_FILE_NAME "slof.bin"
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@ -1580,9 +1579,7 @@ void spapr_setup_hpt(SpaprMachineState *spapr)
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{
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int hpt_shift;
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if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
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|| (spapr->cas_reboot
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&& !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
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if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
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hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
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} else {
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uint64_t current_ram_size;
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@ -1646,16 +1643,10 @@ static void spapr_machine_reset(MachineState *machine)
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qemu_devices_reset();
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/*
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* If this reset wasn't generated by CAS, we should reset our
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* negotiated options and start from scratch
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*/
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if (!spapr->cas_reboot) {
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spapr_ovec_cleanup(spapr->ov5_cas);
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spapr->ov5_cas = spapr_ovec_new();
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spapr_ovec_cleanup(spapr->ov5_cas);
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spapr->ov5_cas = spapr_ovec_new();
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ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
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}
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ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
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/*
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* This is fixing some of the default configuration of the XIVE
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@ -1708,8 +1699,6 @@ static void spapr_machine_reset(MachineState *machine)
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spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);
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first_ppc_cpu->env.gpr[5] = 0;
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spapr->cas_reboot = false;
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spapr->fwnmi_system_reset_addr = -1;
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spapr->fwnmi_machine_check_addr = -1;
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spapr->fwnmi_machine_check_interlock = -1;
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@ -2837,6 +2826,7 @@ static void spapr_machine_init(MachineState *machine)
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if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
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ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
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spapr->max_compat_pvr)) {
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spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300);
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/* KVM and TCG always allow GTSE with radix... */
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spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
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}
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@ -3385,13 +3375,13 @@ static void spapr_machine_finalizefn(Object *obj)
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void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
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{
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SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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cpu_synchronize_state(cs);
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/* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
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if (spapr->fwnmi_system_reset_addr != -1) {
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uint64_t rtas_addr, addr;
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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/* get rtas addr from fdt */
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rtas_addr = spapr_get_rtas_addr();
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@ -3405,7 +3395,10 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
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stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0);
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env->gpr[3] = addr;
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}
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ppc_cpu_do_system_reset(cs, spapr->fwnmi_system_reset_addr);
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ppc_cpu_do_system_reset(cs);
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if (spapr->fwnmi_system_reset_addr != -1) {
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env->nip = spapr->fwnmi_system_reset_addr;
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}
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}
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static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
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@ -1665,23 +1665,20 @@ static void spapr_handle_transient_dev_before_cas(SpaprMachineState *spapr)
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spapr_clear_pending_hotplug_events(spapr);
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}
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static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
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SpaprMachineState *spapr,
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target_ulong opcode,
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target_ulong *args)
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target_ulong do_client_architecture_support(PowerPCCPU *cpu,
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SpaprMachineState *spapr,
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target_ulong vec,
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target_ulong fdt_bufsize)
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{
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/* Working address in data buffer */
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target_ulong addr = ppc64_phys_to_real(args[0]);
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target_ulong fdt_buf = args[1];
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target_ulong fdt_bufsize = args[2];
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target_ulong ov_table;
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target_ulong ov_table; /* Working address in data buffer */
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uint32_t cas_pvr;
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SpaprOptionVector *ov1_guest, *ov5_guest, *ov5_cas_old;
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SpaprOptionVector *ov1_guest, *ov5_guest;
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bool guest_radix;
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Error *local_err = NULL;
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bool raw_mode_supported = false;
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bool guest_xive;
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CPUState *cs;
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void *fdt;
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/* CAS is supposed to be called early when only the boot vCPU is active. */
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CPU_FOREACH(cs) {
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@ -1694,7 +1691,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
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}
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}
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cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err);
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cas_pvr = cas_check_pvr(spapr, cpu, &vec, &raw_mode_supported, &local_err);
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if (local_err) {
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error_report_err(local_err);
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return H_HARDWARE;
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@ -1717,7 +1714,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
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}
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/* For the future use: here @ov_table points to the first option vector */
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ov_table = addr;
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ov_table = vec;
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ov1_guest = spapr_ovec_parse_vector(ov_table, 1);
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if (!ov1_guest) {
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@ -1739,9 +1736,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
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exit(EXIT_FAILURE);
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}
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/* The radix/hash bit in byte 24 requires special handling: */
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guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300);
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spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300);
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guest_xive = spapr_ovec_test(ov5_guest, OV5_XIVE_EXPLOIT);
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@ -1782,30 +1777,16 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
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* by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need
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* to worry about this for now.
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*/
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ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas);
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/* also clear the radix/hash bit from the current ov5_cas bits to
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* be in sync with the newly ov5 bits. Else the radix bit will be
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* seen as being removed and this will generate a reset loop
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*/
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spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300);
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/* full range of negotiated ov5 capabilities */
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spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);
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spapr_ovec_cleanup(ov5_guest);
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/* capabilities that have been added since CAS-generated guest reset.
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* if capabilities have since been removed, generate another reset
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*/
|
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spapr->cas_reboot = !spapr_ovec_subset(ov5_cas_old, spapr->ov5_cas);
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spapr_ovec_cleanup(ov5_cas_old);
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/* Now that processing is finished, set the radix/hash bit for the
|
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* guest if it requested a valid mode; otherwise terminate the boot. */
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|
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if (guest_radix) {
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if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {
|
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error_report("Guest requested unavailable MMU mode (radix).");
|
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exit(EXIT_FAILURE);
|
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}
|
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spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300);
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} else {
|
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if (kvm_enabled() && kvmppc_has_cap_mmu_radix()
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&& !kvmppc_has_cap_mmu_hash_v3()) {
|
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|
|
@ -1838,46 +1819,59 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
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|
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spapr_handle_transient_dev_before_cas(spapr);
|
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|
||||
if (!spapr->cas_reboot) {
|
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void *fdt;
|
||||
SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
|
||||
|
||||
/* If spapr_machine_reset() did not set up a HPT but one is necessary
|
||||
* (because the guest isn't going to use radix) then set it up here. */
|
||||
if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
|
||||
/* legacy hash or new hash: */
|
||||
spapr_setup_hpt(spapr);
|
||||
}
|
||||
|
||||
if (fdt_bufsize < sizeof(hdr)) {
|
||||
error_report("SLOF provided insufficient CAS buffer "
|
||||
TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
fdt_bufsize -= sizeof(hdr);
|
||||
|
||||
fdt = spapr_build_fdt(spapr, false, fdt_bufsize);
|
||||
_FDT((fdt_pack(fdt)));
|
||||
|
||||
cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr));
|
||||
cpu_physical_memory_write(fdt_buf + sizeof(hdr), fdt,
|
||||
fdt_totalsize(fdt));
|
||||
trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
|
||||
|
||||
g_free(spapr->fdt_blob);
|
||||
spapr->fdt_size = fdt_totalsize(fdt);
|
||||
spapr->fdt_initial_size = spapr->fdt_size;
|
||||
spapr->fdt_blob = fdt;
|
||||
/*
|
||||
* If spapr_machine_reset() did not set up a HPT but one is necessary
|
||||
* (because the guest isn't going to use radix) then set it up here.
|
||||
*/
|
||||
if ((spapr->patb_entry & PATE1_GR) && !guest_radix) {
|
||||
/* legacy hash or new hash: */
|
||||
spapr_setup_hpt(spapr);
|
||||
}
|
||||
|
||||
if (spapr->cas_reboot) {
|
||||
qemu_system_reset_request(SHUTDOWN_CAUSE_SUBSYSTEM_RESET);
|
||||
}
|
||||
fdt = spapr_build_fdt(spapr, false, fdt_bufsize);
|
||||
|
||||
g_free(spapr->fdt_blob);
|
||||
spapr->fdt_size = fdt_totalsize(fdt);
|
||||
spapr->fdt_initial_size = spapr->fdt_size;
|
||||
spapr->fdt_blob = fdt;
|
||||
|
||||
return H_SUCCESS;
|
||||
}
|
||||
|
||||
static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
|
||||
SpaprMachineState *spapr,
|
||||
target_ulong opcode,
|
||||
target_ulong *args)
|
||||
{
|
||||
target_ulong vec = ppc64_phys_to_real(args[0]);
|
||||
target_ulong fdt_buf = args[1];
|
||||
target_ulong fdt_bufsize = args[2];
|
||||
target_ulong ret;
|
||||
SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
|
||||
|
||||
if (fdt_bufsize < sizeof(hdr)) {
|
||||
error_report("SLOF provided insufficient CAS buffer "
|
||||
TARGET_FMT_lu " (min: %zu)", fdt_bufsize, sizeof(hdr));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
fdt_bufsize -= sizeof(hdr);
|
||||
|
||||
ret = do_client_architecture_support(cpu, spapr, vec, fdt_bufsize);
|
||||
if (ret == H_SUCCESS) {
|
||||
_FDT((fdt_pack(spapr->fdt_blob)));
|
||||
spapr->fdt_size = fdt_totalsize(spapr->fdt_blob);
|
||||
spapr->fdt_initial_size = spapr->fdt_size;
|
||||
|
||||
cpu_physical_memory_write(fdt_buf, &hdr, sizeof(hdr));
|
||||
cpu_physical_memory_write(fdt_buf + sizeof(hdr), spapr->fdt_blob,
|
||||
spapr->fdt_size);
|
||||
trace_spapr_cas_continue(spapr->fdt_size + sizeof(hdr));
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static target_ulong h_home_node_associativity(PowerPCCPU *cpu,
|
||||
SpaprMachineState *spapr,
|
||||
target_ulong opcode,
|
||||
|
|
|
|||
|
|
@ -37,9 +37,15 @@ void spapr_nvdimm_validate_opts(NVDIMMDevice *nvdimm, uint64_t size,
|
|||
QemuUUID uuid;
|
||||
int ret;
|
||||
|
||||
if (object_property_get_int(OBJECT(nvdimm), NVDIMM_LABEL_SIZE_PROP,
|
||||
&error_abort) == 0) {
|
||||
error_setg(errp, "PAPR requires NVDIMM devices to have label-size set");
|
||||
return;
|
||||
}
|
||||
|
||||
if (size % SPAPR_MINIMUM_SCM_BLOCK_SIZE) {
|
||||
error_setg(errp, "NVDIMM memory size excluding the label area"
|
||||
" must be a multiple of %" PRIu64 "MB",
|
||||
error_setg(errp, "PAPR requires NVDIMM memory size (excluding label)"
|
||||
" to be a multiple of %" PRIu64 "MB",
|
||||
SPAPR_MINIMUM_SCM_BLOCK_SIZE / MiB);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1665,6 +1665,10 @@ static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
|
|||
error_setg(errp, "PCI: Hot unplug of PCI bridges not supported");
|
||||
return;
|
||||
}
|
||||
if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) {
|
||||
error_setg(errp, "PCI: Cannot unplug NVLink2 devices");
|
||||
return;
|
||||
}
|
||||
|
||||
/* ensure any other present functions are pending unplug */
|
||||
if (PCI_FUNC(pdev->devfn) == 0) {
|
||||
|
|
|
|||
|
|
@ -102,6 +102,8 @@ typedef enum {
|
|||
#define SPAPR_CAP_FIXED_CCD 0x03
|
||||
#define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
|
||||
|
||||
#define FDT_MAX_SIZE 0x100000
|
||||
|
||||
typedef struct SpaprCapabilities SpaprCapabilities;
|
||||
struct SpaprCapabilities {
|
||||
uint8_t caps[SPAPR_CAP_NUM];
|
||||
|
|
@ -176,7 +178,6 @@ struct SpaprMachineState {
|
|||
SpaprEventSource *event_sources;
|
||||
|
||||
/* ibm,client-architecture-support option negotiation */
|
||||
bool cas_reboot;
|
||||
bool cas_pre_isa3_guest;
|
||||
SpaprOptionVector *ov5; /* QEMU-supported option vectors */
|
||||
SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
|
||||
|
|
@ -566,6 +567,11 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
|
|||
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
|
||||
target_ulong *args);
|
||||
|
||||
target_ulong do_client_architecture_support(PowerPCCPU *cpu,
|
||||
SpaprMachineState *spapr,
|
||||
target_ulong addr,
|
||||
target_ulong fdt_bufsize);
|
||||
|
||||
/* Virtual Processor Area structure constants */
|
||||
#define VPA_MIN_SIZE 640
|
||||
#define VPA_SIZE_OFFSET 0x4
|
||||
|
|
|
|||
|
|
@ -463,6 +463,9 @@ typedef struct ppc_v3_pate_t {
|
|||
#define DSISR_AMR 0x00200000
|
||||
/* Unsupported Radix Tree Configuration */
|
||||
#define DSISR_R_BADCONFIG 0x00080000
|
||||
#define DSISR_ATOMIC_RC 0x00040000
|
||||
/* Unable to translate address of (guest) pde or process/page table entry */
|
||||
#define DSISR_PRTABLE_FAULT 0x00020000
|
||||
|
||||
/* SRR1 error code fields */
|
||||
|
||||
|
|
@ -1220,7 +1223,7 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
|
|||
int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
|
||||
int cpuid, void *opaque);
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector);
|
||||
void ppc_cpu_do_system_reset(CPUState *cs);
|
||||
void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
|
||||
extern const VMStateDescription vmstate_ppc_cpu;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -57,12 +57,29 @@ static void ppc_hw_interrupt(CPUPPCState *env)
|
|||
#else /* defined(CONFIG_USER_ONLY) */
|
||||
static inline void dump_syscall(CPUPPCState *env)
|
||||
{
|
||||
qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
|
||||
" r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
|
||||
qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
|
||||
" r3=%016" PRIx64 " r4=%016" PRIx64 " r5=%016" PRIx64
|
||||
" r6=%016" PRIx64 " r7=%016" PRIx64 " r8=%016" PRIx64
|
||||
" nip=" TARGET_FMT_lx "\n",
|
||||
ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
|
||||
ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
|
||||
ppc_dump_gpr(env, 6), env->nip);
|
||||
ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
|
||||
ppc_dump_gpr(env, 8), env->nip);
|
||||
}
|
||||
|
||||
static inline void dump_hcall(CPUPPCState *env)
|
||||
{
|
||||
qemu_log_mask(CPU_LOG_INT, "hypercall r3=%016" PRIx64
|
||||
" r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
|
||||
" r7=%016" PRIx64 " r8=%016" PRIx64 " r9=%016" PRIx64
|
||||
" r10=%016" PRIx64 " r11=%016" PRIx64 " r12=%016" PRIx64
|
||||
" nip=" TARGET_FMT_lx "\n",
|
||||
ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
|
||||
ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6),
|
||||
ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
|
||||
ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
|
||||
ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
|
||||
env->nip);
|
||||
}
|
||||
|
||||
static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
|
||||
|
|
@ -379,9 +396,14 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
|
|||
}
|
||||
break;
|
||||
case POWERPC_EXCP_SYSCALL: /* System call exception */
|
||||
dump_syscall(env);
|
||||
lev = env->error_code;
|
||||
|
||||
if ((lev == 1) && cpu->vhyp) {
|
||||
dump_hcall(env);
|
||||
} else {
|
||||
dump_syscall(env);
|
||||
}
|
||||
|
||||
/*
|
||||
* We need to correct the NIP which in this case is supposed
|
||||
* to point to the next instruction
|
||||
|
|
@ -484,9 +506,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
|
|||
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
|
||||
case POWERPC_EXCP_TRACE: /* Trace exception */
|
||||
break;
|
||||
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
|
||||
msr |= env->error_code;
|
||||
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
|
||||
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
|
||||
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
|
||||
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
|
||||
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
|
||||
case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
|
||||
|
|
@ -961,15 +984,12 @@ static void ppc_hw_interrupt(CPUPPCState *env)
|
|||
}
|
||||
}
|
||||
|
||||
void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector)
|
||||
void ppc_cpu_do_system_reset(CPUState *cs)
|
||||
{
|
||||
PowerPCCPU *cpu = POWERPC_CPU(cs);
|
||||
CPUPPCState *env = &cpu->env;
|
||||
|
||||
powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
|
||||
if (vector != -1) {
|
||||
env->nip = vector;
|
||||
}
|
||||
}
|
||||
|
||||
void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
|
||||
|
|
|
|||
|
|
@ -103,9 +103,31 @@ static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr,
|
|||
}
|
||||
}
|
||||
|
||||
static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, int rwx, vaddr eaddr,
|
||||
hwaddr g_raddr, uint32_t cause)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
CPUPPCState *env = &cpu->env;
|
||||
|
||||
if (rwx == 2) { /* H Instruction Storage Interrupt */
|
||||
cs->exception_index = POWERPC_EXCP_HISI;
|
||||
env->spr[SPR_ASDR] = g_raddr;
|
||||
env->error_code = cause;
|
||||
} else { /* H Data Storage Interrupt */
|
||||
cs->exception_index = POWERPC_EXCP_HDSI;
|
||||
if (rwx == 1) { /* Write -> Store */
|
||||
cause |= DSISR_ISSTORE;
|
||||
}
|
||||
env->spr[SPR_HDSISR] = cause;
|
||||
env->spr[SPR_HDAR] = eaddr;
|
||||
env->spr[SPR_ASDR] = g_raddr;
|
||||
env->error_code = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
|
||||
int *fault_cause, int *prot)
|
||||
int *fault_cause, int *prot,
|
||||
bool partition_scoped)
|
||||
{
|
||||
CPUPPCState *env = &cpu->env;
|
||||
const int need_prot[] = { PAGE_READ, PAGE_WRITE, PAGE_EXEC };
|
||||
|
|
@ -121,11 +143,11 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
|
|||
}
|
||||
|
||||
/* Determine permissions allowed by Encoded Access Authority */
|
||||
if ((pte & R_PTE_EAA_PRIV) && msr_pr) { /* Insufficient Privilege */
|
||||
if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && msr_pr) {
|
||||
*prot = 0;
|
||||
} else if (msr_pr || (pte & R_PTE_EAA_PRIV)) {
|
||||
} else if (msr_pr || (pte & R_PTE_EAA_PRIV) || partition_scoped) {
|
||||
*prot = ppc_radix64_get_prot_eaa(pte);
|
||||
} else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) */
|
||||
} else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */
|
||||
*prot = ppc_radix64_get_prot_eaa(pte);
|
||||
*prot &= ppc_radix64_get_prot_amr(cpu); /* Least combined permissions */
|
||||
}
|
||||
|
|
@ -162,44 +184,67 @@ static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte,
|
|||
}
|
||||
}
|
||||
|
||||
static uint64_t ppc_radix64_walk_tree(PowerPCCPU *cpu, vaddr eaddr,
|
||||
uint64_t base_addr, uint64_t nls,
|
||||
hwaddr *raddr, int *psize,
|
||||
int *fault_cause, hwaddr *pte_addr)
|
||||
static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr,
|
||||
uint64_t *pte_addr, uint64_t *nls,
|
||||
int *psize, uint64_t *pte, int *fault_cause)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
uint64_t index, pde;
|
||||
|
||||
if (nls < 5) { /* Directory maps less than 2**5 entries */
|
||||
if (*nls < 5) { /* Directory maps less than 2**5 entries */
|
||||
*fault_cause |= DSISR_R_BADCONFIG;
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Read page <directory/table> entry from guest address space */
|
||||
index = eaddr >> (*psize - nls); /* Shift */
|
||||
index &= ((1UL << nls) - 1); /* Mask */
|
||||
pde = ldq_phys(cs->as, base_addr + (index * sizeof(pde)));
|
||||
if (!(pde & R_PTE_VALID)) { /* Invalid Entry */
|
||||
pde = ldq_phys(as, *pte_addr);
|
||||
if (!(pde & R_PTE_VALID)) { /* Invalid Entry */
|
||||
*fault_cause |= DSISR_NOPTE;
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
*psize -= nls;
|
||||
*pte = pde;
|
||||
*psize -= *nls;
|
||||
if (!(pde & R_PTE_LEAF)) { /* Prepare for next iteration */
|
||||
*nls = pde & R_PDE_NLS;
|
||||
index = eaddr >> (*psize - *nls); /* Shift */
|
||||
index &= ((1UL << *nls) - 1); /* Mask */
|
||||
*pte_addr = (pde & R_PDE_NLB) + (index * sizeof(pde));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Check if Leaf Entry -> Page Table Entry -> Stop the Search */
|
||||
if (pde & R_PTE_LEAF) {
|
||||
uint64_t rpn = pde & R_PTE_RPN;
|
||||
uint64_t mask = (1UL << *psize) - 1;
|
||||
static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr,
|
||||
uint64_t base_addr, uint64_t nls,
|
||||
hwaddr *raddr, int *psize, uint64_t *pte,
|
||||
int *fault_cause, hwaddr *pte_addr)
|
||||
{
|
||||
uint64_t index, pde, rpn , mask;
|
||||
|
||||
/* Or high bits of rpn and low bits to ea to form whole real addr */
|
||||
*raddr = (rpn & ~mask) | (eaddr & mask);
|
||||
*pte_addr = base_addr + (index * sizeof(pde));
|
||||
return pde;
|
||||
if (nls < 5) { /* Directory maps less than 2**5 entries */
|
||||
*fault_cause |= DSISR_R_BADCONFIG;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Next Level of Radix Tree */
|
||||
return ppc_radix64_walk_tree(cpu, eaddr, pde & R_PDE_NLB, pde & R_PDE_NLS,
|
||||
raddr, psize, fault_cause, pte_addr);
|
||||
index = eaddr >> (*psize - nls); /* Shift */
|
||||
index &= ((1UL << nls) - 1); /* Mask */
|
||||
*pte_addr = base_addr + (index * sizeof(pde));
|
||||
do {
|
||||
int ret;
|
||||
|
||||
ret = ppc_radix64_next_level(as, eaddr, pte_addr, &nls, psize, &pde,
|
||||
fault_cause);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
} while (!(pde & R_PTE_LEAF));
|
||||
|
||||
*pte = pde;
|
||||
rpn = pde & R_PTE_RPN;
|
||||
mask = (1UL << *psize) - 1;
|
||||
|
||||
/* Or high bits of rpn and low bits to ea to form whole real addr */
|
||||
*raddr = (rpn & ~mask) | (eaddr & mask);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
|
||||
|
|
@ -212,26 +257,280 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
|
|||
if (lpid == 0 && !msr_hv) {
|
||||
return false;
|
||||
}
|
||||
if ((pate->dw0 & PATE1_R_PRTS) < 5) {
|
||||
return false;
|
||||
}
|
||||
/* More checks ... */
|
||||
return true;
|
||||
}
|
||||
|
||||
static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx,
|
||||
vaddr eaddr, hwaddr g_raddr,
|
||||
ppc_v3_pate_t pate,
|
||||
hwaddr *h_raddr, int *h_prot,
|
||||
int *h_page_size, bool pde_addr,
|
||||
bool cause_excp)
|
||||
{
|
||||
int fault_cause = 0;
|
||||
hwaddr pte_addr;
|
||||
uint64_t pte;
|
||||
|
||||
*h_page_size = PRTBE_R_GET_RTS(pate.dw0);
|
||||
/* No valid pte or access denied due to protection */
|
||||
if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB,
|
||||
pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size,
|
||||
&pte, &fault_cause, &pte_addr) ||
|
||||
ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, h_prot, true)) {
|
||||
if (pde_addr) /* address being translated was that of a guest pde */
|
||||
fault_cause |= DSISR_PRTABLE_FAULT;
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_hsi(cpu, rwx, eaddr, g_raddr, fault_cause);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Update Reference and Change Bits */
|
||||
ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, h_prot);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
|
||||
vaddr eaddr, uint64_t pid,
|
||||
ppc_v3_pate_t pate, hwaddr *g_raddr,
|
||||
int *g_prot, int *g_page_size,
|
||||
bool cause_excp)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
CPUPPCState *env = &cpu->env;
|
||||
uint64_t offset, size, prtbe_addr, prtbe0, base_addr, nls, index, pte;
|
||||
int fault_cause = 0, h_page_size, h_prot;
|
||||
hwaddr h_raddr, pte_addr;
|
||||
int ret;
|
||||
|
||||
/* Index Process Table by PID to Find Corresponding Process Table Entry */
|
||||
offset = pid * sizeof(struct prtb_entry);
|
||||
size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
|
||||
if (offset >= size) {
|
||||
/* offset exceeds size of the process table */
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
prtbe_addr = (pate.dw1 & PATE1_R_PRTB) + offset;
|
||||
|
||||
if (cpu->vhyp) {
|
||||
prtbe0 = ldq_phys(cs->as, prtbe_addr);
|
||||
} else {
|
||||
/*
|
||||
* Process table addresses are subject to partition-scoped
|
||||
* translation
|
||||
*
|
||||
* On a Radix host, the partition-scoped page table for LPID=0
|
||||
* is only used to translate the effective addresses of the
|
||||
* process table entries.
|
||||
*/
|
||||
ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, prtbe_addr,
|
||||
pate, &h_raddr, &h_prot,
|
||||
&h_page_size, 1, 1);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
prtbe0 = ldq_phys(cs->as, h_raddr);
|
||||
}
|
||||
|
||||
/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
|
||||
*g_page_size = PRTBE_R_GET_RTS(prtbe0);
|
||||
base_addr = prtbe0 & PRTBE_R_RPDB;
|
||||
nls = prtbe0 & PRTBE_R_RPDS;
|
||||
if (msr_hv || cpu->vhyp) {
|
||||
/*
|
||||
* Can treat process table addresses as real addresses
|
||||
*/
|
||||
ret = ppc_radix64_walk_tree(cs->as, eaddr & R_EADDR_MASK, base_addr,
|
||||
nls, g_raddr, g_page_size, &pte,
|
||||
&fault_cause, &pte_addr);
|
||||
if (ret) {
|
||||
/* No valid PTE */
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
uint64_t rpn, mask;
|
||||
|
||||
index = (eaddr & R_EADDR_MASK) >> (*g_page_size - nls); /* Shift */
|
||||
index &= ((1UL << nls) - 1); /* Mask */
|
||||
pte_addr = base_addr + (index * sizeof(pte));
|
||||
|
||||
/*
|
||||
* Each process table address is subject to a partition-scoped
|
||||
* translation
|
||||
*/
|
||||
do {
|
||||
ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, pte_addr,
|
||||
pate, &h_raddr, &h_prot,
|
||||
&h_page_size, 1, 1);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = ppc_radix64_next_level(cs->as, eaddr & R_EADDR_MASK, &h_raddr,
|
||||
&nls, g_page_size, &pte, &fault_cause);
|
||||
if (ret) {
|
||||
/* No valid pte */
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
pte_addr = h_raddr;
|
||||
} while (!(pte & R_PTE_LEAF));
|
||||
|
||||
rpn = pte & R_PTE_RPN;
|
||||
mask = (1UL << *g_page_size) - 1;
|
||||
|
||||
/* Or high bits of rpn and low bits to ea to form whole real addr */
|
||||
*g_raddr = (rpn & ~mask) | (eaddr & mask);
|
||||
}
|
||||
|
||||
if (ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)) {
|
||||
/* Access denied due to protection */
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Radix tree translation is a 2 steps translation process:
|
||||
*
|
||||
* 1. Process-scoped translation: Guest Eff Addr -> Guest Real Addr
|
||||
* 2. Partition-scoped translation: Guest Real Addr -> Host Real Addr
|
||||
*
|
||||
* MSR[HV]
|
||||
* +-------------+----------------+---------------+
|
||||
* | | HV = 0 | HV = 1 |
|
||||
* +-------------+----------------+---------------+
|
||||
* | Relocation | Partition | No |
|
||||
* | = Off | Scoped | Translation |
|
||||
* Relocation +-------------+----------------+---------------+
|
||||
* | Relocation | Partition & | Process |
|
||||
* | = On | Process Scoped | Scoped |
|
||||
* +-------------+----------------+---------------+
|
||||
*/
|
||||
static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
|
||||
bool relocation,
|
||||
hwaddr *raddr, int *psizep, int *protp,
|
||||
bool cause_excp)
|
||||
{
|
||||
CPUPPCState *env = &cpu->env;
|
||||
uint64_t lpid = 0, pid = 0;
|
||||
ppc_v3_pate_t pate;
|
||||
int psize, prot;
|
||||
hwaddr g_raddr;
|
||||
|
||||
/* Virtual Mode Access - get the fully qualified address */
|
||||
if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_segi(cpu, rwx, eaddr);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Get Process Table */
|
||||
if (cpu->vhyp) {
|
||||
PPCVirtualHypervisorClass *vhc;
|
||||
vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
||||
vhc->get_pate(cpu->vhyp, &pate);
|
||||
} else {
|
||||
if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
if (!validate_pate(cpu, lpid, &pate)) {
|
||||
if (cause_excp) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
*psizep = INT_MAX;
|
||||
*protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
|
||||
/*
|
||||
* Perform process-scoped translation if relocation enabled.
|
||||
*
|
||||
* - Translates an effective address to a host real address in
|
||||
* quadrants 0 and 3 when HV=1.
|
||||
*
|
||||
* - Translates an effective address to a guest real address.
|
||||
*/
|
||||
if (relocation) {
|
||||
int ret = ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid,
|
||||
pate, &g_raddr, &prot,
|
||||
&psize, cause_excp);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
*psizep = MIN(*psizep, psize);
|
||||
*protp &= prot;
|
||||
} else {
|
||||
g_raddr = eaddr & R_EADDR_MASK;
|
||||
}
|
||||
|
||||
if (cpu->vhyp) {
|
||||
*raddr = g_raddr;
|
||||
} else {
|
||||
/*
|
||||
* Perform partition-scoped translation if !HV or HV access to
|
||||
* quadrants 1 or 2. Translates a guest real address to a host
|
||||
* real address.
|
||||
*/
|
||||
if (lpid || !msr_hv) {
|
||||
int ret;
|
||||
|
||||
ret = ppc_radix64_partition_scoped_xlate(cpu, rwx, eaddr, g_raddr,
|
||||
pate, raddr, &prot, &psize,
|
||||
0, cause_excp);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
*psizep = MIN(*psizep, psize);
|
||||
*protp &= prot;
|
||||
} else {
|
||||
*raddr = g_raddr;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
|
||||
int mmu_idx)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
CPUPPCState *env = &cpu->env;
|
||||
PPCVirtualHypervisorClass *vhc;
|
||||
hwaddr raddr, pte_addr;
|
||||
uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
|
||||
int page_size, prot, fault_cause = 0;
|
||||
ppc_v3_pate_t pate;
|
||||
int page_size, prot;
|
||||
bool relocation;
|
||||
hwaddr raddr;
|
||||
|
||||
assert(!(msr_hv && cpu->vhyp));
|
||||
assert((rwx == 0) || (rwx == 1) || (rwx == 2));
|
||||
|
||||
relocation = ((rwx == 2) && (msr_ir == 1)) || ((rwx != 2) && (msr_dr == 1));
|
||||
/* HV or virtual hypervisor Real Mode Access */
|
||||
if ((msr_hv || cpu->vhyp) &&
|
||||
(((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0)))) {
|
||||
if (!relocation && (msr_hv || cpu->vhyp)) {
|
||||
/* In real mode top 4 effective addr bits (mostly) ignored */
|
||||
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
|
||||
|
||||
|
|
@ -257,55 +556,12 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
|
|||
TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
|
||||
}
|
||||
|
||||
/* Virtual Mode Access - get the fully qualified address */
|
||||
if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
|
||||
ppc_radix64_raise_segi(cpu, rwx, eaddr);
|
||||
/* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
|
||||
if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr,
|
||||
&page_size, &prot, true)) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Get Process Table */
|
||||
if (cpu->vhyp) {
|
||||
vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
||||
vhc->get_pate(cpu->vhyp, &pate);
|
||||
} else {
|
||||
if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
|
||||
return 1;
|
||||
}
|
||||
if (!validate_pate(cpu, lpid, &pate)) {
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
|
||||
}
|
||||
/* We don't support guest mode yet */
|
||||
if (lpid != 0) {
|
||||
error_report("PowerNV guest support Unimplemented");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Index Process Table by PID to Find Corresponding Process Table Entry */
|
||||
offset = pid * sizeof(struct prtb_entry);
|
||||
size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
|
||||
if (offset >= size) {
|
||||
/* offset exceeds size of the process table */
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
|
||||
return 1;
|
||||
}
|
||||
prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
|
||||
|
||||
/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
|
||||
page_size = PRTBE_R_GET_RTS(prtbe0);
|
||||
pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
|
||||
prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
|
||||
&raddr, &page_size, &fault_cause, &pte_addr);
|
||||
if (!pte || ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, &prot)) {
|
||||
/* Couldn't get pte or access denied due to protection */
|
||||
ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Update Reference and Change Bits */
|
||||
ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, &prot);
|
||||
|
||||
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
|
||||
prot, mmu_idx, 1UL << page_size);
|
||||
return 0;
|
||||
|
|
@ -313,58 +569,18 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
|
|||
|
||||
hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
CPUPPCState *env = &cpu->env;
|
||||
PPCVirtualHypervisorClass *vhc;
|
||||
hwaddr raddr, pte_addr;
|
||||
uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
|
||||
int page_size, fault_cause = 0;
|
||||
ppc_v3_pate_t pate;
|
||||
int psize, prot;
|
||||
hwaddr raddr;
|
||||
|
||||
/* Handle Real Mode */
|
||||
if (msr_dr == 0) {
|
||||
if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) {
|
||||
/* In real mode top 4 effective addr bits (mostly) ignored */
|
||||
return eaddr & 0x0FFFFFFFFFFFFFFFULL;
|
||||
}
|
||||
|
||||
/* Virtual Mode Access - get the fully qualified address */
|
||||
if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Get Process Table */
|
||||
if (cpu->vhyp) {
|
||||
vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
|
||||
vhc->get_pate(cpu->vhyp, &pate);
|
||||
} else {
|
||||
if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
|
||||
return -1;
|
||||
}
|
||||
if (!validate_pate(cpu, lpid, &pate)) {
|
||||
return -1;
|
||||
}
|
||||
/* We don't support guest mode yet */
|
||||
if (lpid != 0) {
|
||||
error_report("PowerNV guest support Unimplemented");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Index Process Table by PID to Find Corresponding Process Table Entry */
|
||||
offset = pid * sizeof(struct prtb_entry);
|
||||
size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
|
||||
if (offset >= size) {
|
||||
/* offset exceeds size of the process table */
|
||||
return -1;
|
||||
}
|
||||
prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
|
||||
|
||||
/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
|
||||
page_size = PRTBE_R_GET_RTS(prtbe0);
|
||||
pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
|
||||
prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
|
||||
&raddr, &page_size, &fault_cause, &pte_addr);
|
||||
if (!pte) {
|
||||
if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize,
|
||||
&prot, false)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1882,6 +1882,7 @@ static void gen_rlwimi(DisasContext *ctx)
|
|||
tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
|
||||
} else {
|
||||
target_ulong mask;
|
||||
bool mask_in_32b = true;
|
||||
TCGv t1;
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
|
|
@ -1890,8 +1891,13 @@ static void gen_rlwimi(DisasContext *ctx)
|
|||
#endif
|
||||
mask = MASK(mb, me);
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
if (mask > 0xffffffffu) {
|
||||
mask_in_32b = false;
|
||||
}
|
||||
#endif
|
||||
t1 = tcg_temp_new();
|
||||
if (mask <= 0xffffffffu) {
|
||||
if (mask_in_32b) {
|
||||
TCGv_i32 t0 = tcg_temp_new_i32();
|
||||
tcg_gen_trunc_tl_i32(t0, t_rs);
|
||||
tcg_gen_rotli_i32(t0, t0, sh);
|
||||
|
|
@ -1933,12 +1939,18 @@ static void gen_rlwinm(DisasContext *ctx)
|
|||
tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
|
||||
} else {
|
||||
target_ulong mask;
|
||||
bool mask_in_32b = true;
|
||||
#if defined(TARGET_PPC64)
|
||||
mb += 32;
|
||||
me += 32;
|
||||
#endif
|
||||
mask = MASK(mb, me);
|
||||
if (mask <= 0xffffffffu) {
|
||||
#if defined(TARGET_PPC64)
|
||||
if (mask > 0xffffffffu) {
|
||||
mask_in_32b = false;
|
||||
}
|
||||
#endif
|
||||
if (mask_in_32b) {
|
||||
if (sh == 0) {
|
||||
tcg_gen_andi_tl(t_ra, t_rs, mask);
|
||||
} else {
|
||||
|
|
@ -1973,6 +1985,7 @@ static void gen_rlwnm(DisasContext *ctx)
|
|||
uint32_t mb = MB(ctx->opcode);
|
||||
uint32_t me = ME(ctx->opcode);
|
||||
target_ulong mask;
|
||||
bool mask_in_32b = true;
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
mb += 32;
|
||||
|
|
@ -1980,7 +1993,12 @@ static void gen_rlwnm(DisasContext *ctx)
|
|||
#endif
|
||||
mask = MASK(mb, me);
|
||||
|
||||
if (mask <= 0xffffffffu) {
|
||||
#if defined(TARGET_PPC64)
|
||||
if (mask > 0xffffffffu) {
|
||||
mask_in_32b = false;
|
||||
}
|
||||
#endif
|
||||
if (mask_in_32b) {
|
||||
TCGv_i32 t0 = tcg_temp_new_i32();
|
||||
TCGv_i32 t1 = tcg_temp_new_i32();
|
||||
tcg_gen_trunc_tl_i32(t0, t_rb);
|
||||
|
|
|
|||
Loading…
Reference in a new issue