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hw/alpha/typhoon: Stop calling cpu_unassigned_access()
The typhoon MemoryRegionOps callbacks directly call
cpu_unassigned_access(), presumably as the old-fashioned way
to provoke a CPU exception. This won't work since commit
6ad4d7eed0
when we switched Alpha over to the
transaction_failed hook API, because now cpu_unassigned_access()
is a no-op for Alpha.
Make the MemoryRegionOps callbacks use the read_with_attrs
and write_with_attrs hooks, so they can signal a failure
that should cause a CPU exception by returning MEMTX_ERROR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20181210173350.13073-1-peter.maydell@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
c102d9471f
commit
b7ed683a8d
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@ -75,7 +75,9 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
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}
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}
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static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
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static MemTxResult cchip_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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CPUState *cpu = current_cpu;
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TyphoonState *s = opaque;
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@ -196,11 +198,11 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size)
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break;
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default:
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cpu_unassigned_access(cpu, addr, false, false, 0, size);
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return -1;
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return MEMTX_ERROR;
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}
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return ret;
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*data = ret;
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return MEMTX_OK;
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}
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static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
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@ -209,7 +211,8 @@ static uint64_t dchip_read(void *opaque, hwaddr addr, unsigned size)
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return 0;
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}
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static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
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static MemTxResult pchip_read(void *opaque, hwaddr addr, uint64_t *data,
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unsigned size, MemTxAttrs attrs)
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{
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TyphoonState *s = opaque;
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uint64_t ret = 0;
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@ -294,15 +297,16 @@ static uint64_t pchip_read(void *opaque, hwaddr addr, unsigned size)
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break;
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default:
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cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
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return -1;
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return MEMTX_ERROR;
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}
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return ret;
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*data = ret;
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return MEMTX_OK;
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}
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static void cchip_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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static MemTxResult cchip_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size,
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MemTxAttrs attrs)
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{
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TyphoonState *s = opaque;
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uint64_t oldval, newval;
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@ -446,9 +450,10 @@ static void cchip_write(void *opaque, hwaddr addr,
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break;
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default:
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cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
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return;
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return MEMTX_ERROR;
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}
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return MEMTX_OK;
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}
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static void dchip_write(void *opaque, hwaddr addr,
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@ -457,8 +462,9 @@ static void dchip_write(void *opaque, hwaddr addr,
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/* Skip this. It's all related to DRAM timing and setup. */
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}
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static void pchip_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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static MemTxResult pchip_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size,
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MemTxAttrs attrs)
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{
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TyphoonState *s = opaque;
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uint64_t oldval;
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@ -553,14 +559,15 @@ static void pchip_write(void *opaque, hwaddr addr,
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break;
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default:
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cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
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return;
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return MEMTX_ERROR;
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps cchip_ops = {
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.read = cchip_read,
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.write = cchip_write,
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.read_with_attrs = cchip_read,
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.write_with_attrs = cchip_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 8,
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@ -587,8 +594,8 @@ static const MemoryRegionOps dchip_ops = {
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};
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static const MemoryRegionOps pchip_ops = {
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.read = pchip_read,
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.write = pchip_write,
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.read_with_attrs = pchip_read,
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.write_with_attrs = pchip_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 8,
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