mirror of
https://gitlab.com/qemu-project/qemu
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* Fix stack-overflow due to recursive DMA in intel-hda (CVE-2021-3611)
* Fix heap overflow due to recursive DMA in sdhci code -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmI4pGwRHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbXF5xAAq4rPbi4f0eQ1AkEgfnUgnbgg48UoHvkQ 8de1QoVO8Jo88MJgDF0hPirW7SQUpiTrxGpGIBdQOqqq9E41Sz1UEyaNM3SLoGpX N+Dbt+70H/yro0E0XiPmoUEOlKPIqENaS5dzLm6xVI/zA05vAw5JFXgQ6KvcYK2X YQvUyYoPmKMah6TSJrXbtgieKjkutnhoNIkLawulBP8BRuROhKYFDRsBFMAKlqmT m/FHGmkrLEVUVG3Uj5nqR+IKjLrPjFWLUuLLMATm8N5+umQwffTFeUw7ZrjDQ700 T8ciLwO/zRLXvkOeAGXhP1uEmShlflRyN9pK+Cgl2DkdilMB0aMwRQEnLFbnCCzy 6O2lfoo4tXwJAJ/uoOP7auT/RO0hX554s4da2T7SjI42XZwaZszihMKdoC0BFi06 jwrmomLFSdPz4eDdxFg7zl2ugcoBlmAif1aRXfFs1AquTVwTkicD/n2Av9hj8eyF 8vDkqJHzgoCWU+5Intuv32KgkUcZPK/Qqp8u8xRKUrwekeb/Iovh9qGO3iHKMAh3 aAi//QByhtEBjgDEVq6E/OMjfvOD3QbJv9PzDTTdUyRGx0e4/3iOTspzpA3gl/zB q4tFtTiisbRIgBCVl4/R0El76FsGTr56vGwsncsJskx7BLLZuSIb48Hqb7euUdO9 SHFcvADZKAI= =/FY+ -----END PGP SIGNATURE----- Merge tag 'pull-request-2022-03-21' of https://gitlab.com/thuth/qemu into staging * Fix stack-overflow due to recursive DMA in intel-hda (CVE-2021-3611) * Fix heap overflow due to recursive DMA in sdhci code # gpg: Signature made Mon 21 Mar 2022 16:14:36 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-03-21' of https://gitlab.com/thuth/qemu: tests/qtest/fuzz-sdcard-test: Add reproducer for OSS-Fuzz (Issue 29225) hw/sd/sdhci: Prohibit DMA accesses to devices hw/sd/sdhci: Honor failed DMA transactions tests/qtest/intel-hda-test: Add reproducer for issue #542 hw/audio/intel-hda: Restrict DMA engine to memories (not MMIO devices) hw/audio/intel-hda: Do not ignore DMA overrun errors softmmu/physmem: Introduce MemTxAttrs::memory field and MEMTX_ACCESS_ERROR softmmu/physmem: Simplify flatview_write and address_space_access_valid Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
b7a3a705b6
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@ -345,11 +345,12 @@ static void intel_hda_corb_run(IntelHDAState *d)
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static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
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{
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const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
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const MemTxAttrs attrs = { .memory = true };
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HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
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IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
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hwaddr addr;
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uint32_t wp, ex;
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MemTxResult res = MEMTX_OK;
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if (d->ics & ICH6_IRS_BUSY) {
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dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
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@ -368,8 +369,12 @@ static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t res
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ex = (solicited ? 0 : (1 << 4)) | dev->cad;
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wp = (d->rirb_wp + 1) & 0xff;
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addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
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stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs);
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stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs);
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res |= stl_le_pci_dma(&d->pci, addr + 8 * wp, response, attrs);
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res |= stl_le_pci_dma(&d->pci, addr + 8 * wp + 4, ex, attrs);
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if (res != MEMTX_OK && (d->rirb_ctl & ICH6_RBCTL_OVERRUN_EN)) {
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d->rirb_sts |= ICH6_RBSTS_OVERRUN;
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intel_hda_update_irq(d);
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}
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d->rirb_wp = wp;
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dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
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@ -741,7 +741,9 @@ static void sdhci_do_adma(SDHCIState *s)
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{
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unsigned int begin, length;
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const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
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const MemTxAttrs attrs = { .memory = true };
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ADMADescr dscr = {};
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MemTxResult res;
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int i;
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if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) {
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@ -790,10 +792,13 @@ static void sdhci_do_adma(SDHCIState *s)
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s->data_count = block_size;
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length -= block_size - begin;
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}
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dma_memory_write(s->dma_as, dscr.addr,
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&s->fifo_buffer[begin],
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s->data_count - begin,
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MEMTXATTRS_UNSPECIFIED);
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res = dma_memory_write(s->dma_as, dscr.addr,
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&s->fifo_buffer[begin],
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s->data_count - begin,
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attrs);
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if (res != MEMTX_OK) {
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break;
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}
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dscr.addr += s->data_count - begin;
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if (s->data_count == block_size) {
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s->data_count = 0;
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@ -816,10 +821,13 @@ static void sdhci_do_adma(SDHCIState *s)
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s->data_count = block_size;
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length -= block_size - begin;
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}
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dma_memory_read(s->dma_as, dscr.addr,
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&s->fifo_buffer[begin],
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s->data_count - begin,
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MEMTXATTRS_UNSPECIFIED);
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res = dma_memory_read(s->dma_as, dscr.addr,
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&s->fifo_buffer[begin],
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s->data_count - begin,
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attrs);
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if (res != MEMTX_OK) {
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break;
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}
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dscr.addr += s->data_count - begin;
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if (s->data_count == block_size) {
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sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
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@ -833,7 +841,16 @@ static void sdhci_do_adma(SDHCIState *s)
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}
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}
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}
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s->admasysaddr += dscr.incr;
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if (res != MEMTX_OK) {
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if (s->errintstsen & SDHC_EISEN_ADMAERR) {
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trace_sdhci_error("Set ADMA error flag");
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s->errintsts |= SDHC_EIS_ADMAERR;
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s->norintsts |= SDHC_NIS_ERR;
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}
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sdhci_update_irq(s);
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} else {
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s->admasysaddr += dscr.incr;
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}
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break;
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case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
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s->admasysaddr = dscr.addr;
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@ -35,6 +35,14 @@ typedef struct MemTxAttrs {
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unsigned int secure:1;
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/* Memory access is usermode (unprivileged) */
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unsigned int user:1;
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/*
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* Bus interconnect and peripherals can access anything (memories,
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* devices) by default. By setting the 'memory' bit, bus transaction
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* are restricted to "normal" memories (per the AMBA documentation)
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* versus devices. Access to devices will be logged and rejected
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* (see MEMTX_ACCESS_ERROR).
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*/
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unsigned int memory:1;
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/* Requester ID (for MSI for example) */
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unsigned int requester_id:16;
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/* Invert endianness for this page */
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@ -66,6 +74,7 @@ typedef struct MemTxAttrs {
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#define MEMTX_OK 0
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#define MEMTX_ERROR (1U << 0) /* device returned an error */
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#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
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#define MEMTX_ACCESS_ERROR (1U << 2) /* access denied */
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typedef uint32_t MemTxResult;
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#endif
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@ -42,6 +42,7 @@
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#include "qemu/config-file.h"
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#include "qemu/error-report.h"
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#include "qemu/qemu-print.h"
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#include "qemu/log.h"
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#include "qemu/memalign.h"
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#include "exec/memory.h"
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#include "exec/ioport.h"
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@ -2760,6 +2761,33 @@ static bool prepare_mmio_access(MemoryRegion *mr)
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return release_lock;
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}
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/**
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* flatview_access_allowed
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* @mr: #MemoryRegion to be accessed
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* @attrs: memory transaction attributes
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* @addr: address within that memory region
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* @len: the number of bytes to access
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*
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* Check if a memory transaction is allowed.
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*
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* Returns: true if transaction is allowed, false if denied.
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*/
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static bool flatview_access_allowed(MemoryRegion *mr, MemTxAttrs attrs,
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hwaddr addr, hwaddr len)
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{
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if (likely(!attrs.memory)) {
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return true;
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}
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if (memory_region_is_ram(mr)) {
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return true;
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"Invalid access to non-RAM device at "
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"addr 0x%" HWADDR_PRIX ", size %" HWADDR_PRIu ", "
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"region '%s'\n", addr, len, memory_region_name(mr));
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return false;
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}
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/* Called within RCU critical section. */
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static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
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MemTxAttrs attrs,
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@ -2774,7 +2802,10 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
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const uint8_t *buf = ptr;
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for (;;) {
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if (!memory_access_is_direct(mr, true)) {
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if (!flatview_access_allowed(mr, attrs, addr1, l)) {
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result |= MEMTX_ACCESS_ERROR;
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/* Keep going. */
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} else if (!memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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l = memory_access_size(mr, l, addr1);
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/* XXX: could force current_cpu to NULL to avoid
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@ -2816,14 +2847,14 @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
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hwaddr l;
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hwaddr addr1;
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MemoryRegion *mr;
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MemTxResult result = MEMTX_OK;
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l = len;
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mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
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result = flatview_write_continue(fv, addr, attrs, buf, len,
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addr1, l, mr);
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return result;
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if (!flatview_access_allowed(mr, attrs, addr, len)) {
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return MEMTX_ACCESS_ERROR;
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}
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return flatview_write_continue(fv, addr, attrs, buf, len,
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addr1, l, mr);
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}
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/* Called within RCU critical section. */
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@ -2840,7 +2871,10 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
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fuzz_dma_read_cb(addr, len, mr);
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for (;;) {
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if (!memory_access_is_direct(mr, false)) {
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if (!flatview_access_allowed(mr, attrs, addr1, l)) {
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result |= MEMTX_ACCESS_ERROR;
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/* Keep going. */
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} else if (!memory_access_is_direct(mr, false)) {
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/* I/O case */
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release_lock |= prepare_mmio_access(mr);
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l = memory_access_size(mr, l, addr1);
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@ -2883,6 +2917,9 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
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l = len;
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mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
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if (!flatview_access_allowed(mr, attrs, addr, len)) {
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return MEMTX_ACCESS_ERROR;
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}
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return flatview_read_continue(fv, addr, attrs, buf, len,
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addr1, l, mr);
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}
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@ -3139,12 +3176,10 @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
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MemTxAttrs attrs)
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{
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FlatView *fv;
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bool result;
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RCU_READ_LOCK_GUARD();
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fv = address_space_to_flatview(as);
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result = flatview_access_valid(fv, addr, len, is_write, attrs);
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return result;
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return flatview_access_valid(fv, addr, len, is_write, attrs);
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}
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static hwaddr
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@ -87,6 +87,81 @@ static void oss_fuzz_36217(void)
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qtest_quit(s);
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}
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/*
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* https://gitlab.com/qemu-project/qemu/-/issues/451
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* Used to trigger a heap buffer overflow.
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*/
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static void oss_fuzz_36391(void)
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{
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QTestState *s;
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s = qtest_init(" -display none -m 512M -nodefaults -nographic"
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" -device sdhci-pci,sd-spec-version=3"
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" -device sd-card,drive=drv"
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" -drive if=none,index=0,file=null-co://,format=raw,id=drv");
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qtest_outl(s, 0xcf8, 0x80001010);
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qtest_outl(s, 0xcfc, 0xe0000000);
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qtest_outl(s, 0xcf8, 0x80001004);
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qtest_outw(s, 0xcfc, 0x7);
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qtest_bufwrite(s, 0xe0000005, "\x73", 0x1);
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qtest_bufwrite(s, 0xe0000028, "\x55", 0x1);
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qtest_bufwrite(s, 0xe000002c, "\x55", 0x1);
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qtest_bufwrite(s, 0x0, "\x65", 0x1);
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qtest_bufwrite(s, 0x7, "\x69", 0x1);
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qtest_bufwrite(s, 0x8, "\x65", 0x1);
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qtest_bufwrite(s, 0xf, "\x69", 0x1);
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qtest_bufwrite(s, 0x10, "\x65", 0x1);
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qtest_bufwrite(s, 0x17, "\x69", 0x1);
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qtest_bufwrite(s, 0x18, "\x65", 0x1);
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qtest_bufwrite(s, 0x1f, "\x69", 0x1);
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qtest_bufwrite(s, 0x20, "\x65", 0x1);
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qtest_bufwrite(s, 0x27, "\x69", 0x1);
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qtest_bufwrite(s, 0x28, "\x65", 0x1);
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qtest_bufwrite(s, 0x2f, "\x69", 0x1);
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qtest_bufwrite(s, 0x30, "\x65", 0x1);
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qtest_bufwrite(s, 0x37, "\x69", 0x1);
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qtest_bufwrite(s, 0x38, "\x65", 0x1);
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qtest_bufwrite(s, 0x3f, "\x69", 0x1);
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qtest_bufwrite(s, 0x40, "\x65", 0x1);
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qtest_bufwrite(s, 0x47, "\x69", 0x1);
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qtest_bufwrite(s, 0x48, "\x65", 0x1);
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qtest_bufwrite(s, 0xe000000c, "\x55", 0x1);
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qtest_bufwrite(s, 0xe000000e, "\x2c", 0x1);
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qtest_bufwrite(s, 0xe000000f, "\x5b", 0x1);
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qtest_bufwrite(s, 0xe0000010, "\x06\x46", 0x2);
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qtest_bufwrite(s, 0x50, "\x65", 0x1);
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qtest_bufwrite(s, 0x57, "\x69", 0x1);
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qtest_bufwrite(s, 0x58, "\x65", 0x1);
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qtest_bufwrite(s, 0x5f, "\x69", 0x1);
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qtest_bufwrite(s, 0x60, "\x65", 0x1);
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qtest_bufwrite(s, 0x67, "\x69", 0x1);
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qtest_bufwrite(s, 0x68, "\x65", 0x1);
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qtest_bufwrite(s, 0x6f, "\x69", 0x1);
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qtest_bufwrite(s, 0x70, "\x65", 0x1);
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qtest_bufwrite(s, 0x77, "\x69", 0x1);
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qtest_bufwrite(s, 0x78, "\x65", 0x1);
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qtest_bufwrite(s, 0x7f, "\x69", 0x1);
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qtest_bufwrite(s, 0x80, "\x65", 0x1);
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qtest_bufwrite(s, 0x87, "\x69", 0x1);
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qtest_bufwrite(s, 0x88, "\x65", 0x1);
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qtest_bufwrite(s, 0x8f, "\x69", 0x1);
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qtest_bufwrite(s, 0x90, "\x65", 0x1);
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qtest_bufwrite(s, 0x97, "\x69", 0x1);
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qtest_bufwrite(s, 0x98, "\x65", 0x1);
|
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qtest_bufwrite(s, 0xe0000026, "\x5a\x06", 0x2);
|
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qtest_bufwrite(s, 0xe0000028, "\x46\xc0\xc9\xc9", 0x4);
|
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qtest_bufwrite(s, 0xe0000028, "\x55", 0x1);
|
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qtest_bufwrite(s, 0xe000002a, "\x5a", 0x1);
|
||||
qtest_bufwrite(s, 0xa0, "\x65", 0x1);
|
||||
qtest_bufwrite(s, 0xa5, "\xff", 0x1);
|
||||
qtest_bufwrite(s, 0xa6, "\xff", 0x1);
|
||||
qtest_bufwrite(s, 0xa7, "\xdf", 0x1);
|
||||
qtest_bufwrite(s, 0xe000000c, "\x27", 0x1);
|
||||
qtest_bufwrite(s, 0xe000000f, "\x55", 0x1);
|
||||
|
||||
qtest_quit(s);
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
const char *arch = qtest_get_arch();
|
||||
|
|
@ -96,6 +171,7 @@ int main(int argc, char **argv)
|
|||
if (strcmp(arch, "i386") == 0) {
|
||||
qtest_add_func("fuzz/sdcard/oss_fuzz_29225", oss_fuzz_29225);
|
||||
qtest_add_func("fuzz/sdcard/oss_fuzz_36217", oss_fuzz_36217);
|
||||
qtest_add_func("fuzz/sdcard/oss_fuzz_36391", oss_fuzz_36391);
|
||||
}
|
||||
|
||||
return g_test_run();
|
||||
|
|
|
|||
|
|
@ -29,11 +29,45 @@ static void ich9_test(void)
|
|||
qtest_end();
|
||||
}
|
||||
|
||||
/*
|
||||
* https://gitlab.com/qemu-project/qemu/-/issues/542
|
||||
* Used to trigger:
|
||||
* AddressSanitizer: stack-overflow
|
||||
*/
|
||||
static void test_issue542_ich6(void)
|
||||
{
|
||||
QTestState *s;
|
||||
|
||||
s = qtest_init("-nographic -nodefaults -M pc-q35-6.2 "
|
||||
"-device intel-hda,id=" HDA_ID CODEC_DEVICES);
|
||||
|
||||
qtest_outl(s, 0xcf8, 0x80000804);
|
||||
qtest_outw(s, 0xcfc, 0x06);
|
||||
qtest_bufwrite(s, 0xff0d060f, "\x03", 1);
|
||||
qtest_bufwrite(s, 0x0, "\x12", 1);
|
||||
qtest_bufwrite(s, 0x2, "\x2a", 1);
|
||||
qtest_writeb(s, 0x0, 0x12);
|
||||
qtest_writeb(s, 0x2, 0x2a);
|
||||
qtest_outl(s, 0xcf8, 0x80000811);
|
||||
qtest_outl(s, 0xcfc, 0x006a4400);
|
||||
qtest_bufwrite(s, 0x6a44005a, "\x01", 1);
|
||||
qtest_bufwrite(s, 0x6a44005c, "\x02", 1);
|
||||
qtest_bufwrite(s, 0x6a442050, "\x00\x00\x44\x6a", 4);
|
||||
qtest_bufwrite(s, 0x6a44204a, "\x01", 1);
|
||||
qtest_bufwrite(s, 0x6a44204c, "\x02", 1);
|
||||
qtest_bufwrite(s, 0x6a44005c, "\x02", 1);
|
||||
qtest_bufwrite(s, 0x6a442050, "\x00\x00\x44\x6a", 4);
|
||||
qtest_bufwrite(s, 0x6a44204a, "\x01", 1);
|
||||
qtest_bufwrite(s, 0x6a44204c, "\x02", 1);
|
||||
qtest_quit(s);
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
g_test_init(&argc, &argv, NULL);
|
||||
qtest_add_func("/intel-hda/ich6", ich6_test);
|
||||
qtest_add_func("/intel-hda/ich9", ich9_test);
|
||||
qtest_add_func("/intel-hda/fuzz/issue542", test_issue542_ich6);
|
||||
|
||||
return g_test_run();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue