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target/nios2: Rewrite interrupt handling
Previously, we would avoid setting CPU_INTERRUPT_HARD when interrupts are disabled at a particular point in time, instead queuing the value into cpu->irq_pending. This is more complicated than required. Instead, set CPU_INTERRUPT_HARD any time there is a pending interrupt, and exclusively check for interrupts disabled in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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8d8d73b551
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5 changed files with 9 additions and 36 deletions
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@ -73,12 +73,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level)
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env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
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env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level);
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env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE];
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if (env->regs[CR_IPENDING]) {
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if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) {
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env->irq_pending = 0;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else if (!env->irq_pending) {
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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}
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@ -134,7 +131,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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CPUNios2State *env = &cpu->env;
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CPUNios2State *env = &cpu->env;
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(env->regs[CR_STATUS] & CR_STATUS_PIE)) {
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(env->regs[CR_STATUS] & CR_STATUS_PIE) &&
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(env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) {
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cs->exception_index = EXCP_IRQ;
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cs->exception_index = EXCP_IRQ;
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nios2_cpu_do_interrupt(cs);
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nios2_cpu_do_interrupt(cs);
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return true;
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return true;
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@ -160,7 +160,6 @@ struct CPUNios2State {
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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Nios2MMU mmu;
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Nios2MMU mmu;
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uint32_t irq_pending;
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#endif
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#endif
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int error_code;
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int error_code;
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};
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};
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@ -24,5 +24,4 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
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DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
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DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
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DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
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DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
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DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
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DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
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DEF_HELPER_1(check_interrupts, void, env)
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#endif
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#endif
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@ -21,28 +21,9 @@
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#include "qemu/osdep.h"
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "qemu/main-loop.h"
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#include "qemu/main-loop.h"
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#if !defined(CONFIG_USER_ONLY)
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static void nios2_check_interrupts(CPUNios2State *env)
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{
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if (env->irq_pending &&
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(env->regs[CR_STATUS] & CR_STATUS_PIE)) {
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env->irq_pending = 0;
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cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD);
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}
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}
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void helper_check_interrupts(CPUNios2State *env)
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{
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qemu_mutex_lock_iothread();
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nios2_check_interrupts(env);
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qemu_mutex_unlock_iothread();
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}
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#endif /* !CONFIG_USER_ONLY */
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void helper_raise_exception(CPUNios2State *env, uint32_t index)
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void helper_raise_exception(CPUNios2State *env, uint32_t index)
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{
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{
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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@ -491,19 +491,15 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
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case CR_IPENDING:
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case CR_IPENDING:
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/* ipending is read only, writes ignored. */
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/* ipending is read only, writes ignored. */
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break;
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break;
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case CR_STATUS:
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case CR_IENABLE:
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/* If interrupts were enabled using WRCTL, trigger them. */
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dc->base.is_jmp = DISAS_UPDATE;
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/* fall through */
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default:
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default:
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tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
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tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
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break;
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break;
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}
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}
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/* If interrupts were enabled using WRCTL, trigger them. */
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if ((instr.imm5 + CR_BASE) == CR_STATUS) {
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_check_interrupts(cpu_env);
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dc->base.is_jmp = DISAS_UPDATE;
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}
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#endif
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#endif
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}
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}
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