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hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
The GIC_BASE_IRQ macro is a leftover from when we shared code between the GICv2 and the v7M NVIC. Since the NVIC is now split off, GIC_BASE_IRQ is always 0, and we can just delete it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180824161819.11085-1-peter.maydell@linaro.org
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48314d8316
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b6e6c65151
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@ -955,7 +955,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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res = 0;
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if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
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/* Every byte offset holds 8 group status bits */
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irq = (offset - 0x080) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x080) * 8;
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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@ -974,7 +974,6 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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irq = (offset - 0x100) * 8;
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else
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irq = (offset - 0x180) * 8;
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irq += GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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@ -994,7 +993,6 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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irq = (offset - 0x200) * 8;
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else
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irq = (offset - 0x280) * 8;
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irq += GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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@ -1019,7 +1017,6 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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goto bad_reg;
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}
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irq += GIC_BASE_IRQ;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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@ -1036,7 +1033,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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}
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} else if (offset < 0x800) {
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/* Interrupt Priority. */
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irq = (offset - 0x400) + GIC_BASE_IRQ;
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irq = (offset - 0x400);
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if (irq >= s->num_irq)
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goto bad_reg;
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res = gic_dist_get_priority(s, cpu, irq, attrs);
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@ -1046,7 +1043,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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/* For uniprocessor GICs these RAZ/WI */
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res = 0;
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} else {
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irq = (offset - 0x800) + GIC_BASE_IRQ;
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irq = (offset - 0x800);
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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@ -1060,7 +1057,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
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}
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
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irq = (offset - 0xc00) * 4;
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if (irq >= s->num_irq)
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goto bad_reg;
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res = 0;
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@ -1183,7 +1180,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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*/
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if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
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/* Every byte offset holds 8 group status bits */
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irq = (offset - 0x80) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x80) * 8;
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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@ -1204,7 +1201,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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}
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} else if (offset < 0x180) {
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/* Interrupt Set Enable. */
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irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x100) * 8;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_NR_SGIS) {
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@ -1239,7 +1236,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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}
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} else if (offset < 0x200) {
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/* Interrupt Clear Enable. */
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irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x180) * 8;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_NR_SGIS) {
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@ -1264,7 +1261,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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}
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} else if (offset < 0x280) {
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/* Interrupt Set Pending. */
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irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x200) * 8;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_NR_SGIS) {
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@ -1283,7 +1280,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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}
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} else if (offset < 0x300) {
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/* Interrupt Clear Pending. */
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irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x280) * 8;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_NR_SGIS) {
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@ -1309,7 +1306,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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goto bad_reg;
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}
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irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x300) * 8;
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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@ -1333,7 +1330,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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goto bad_reg;
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}
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irq = (offset - 0x380) * 8 + GIC_BASE_IRQ;
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irq = (offset - 0x380) * 8;
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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@ -1353,7 +1350,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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}
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} else if (offset < 0x800) {
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/* Interrupt Priority. */
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irq = (offset - 0x400) + GIC_BASE_IRQ;
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irq = (offset - 0x400);
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if (irq >= s->num_irq)
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goto bad_reg;
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gic_dist_set_priority(s, cpu, irq, value, attrs);
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@ -1362,7 +1359,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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* annoying exception of the 11MPCore's GIC.
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*/
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if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
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irq = (offset - 0x800) + GIC_BASE_IRQ;
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irq = (offset - 0x800);
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if (irq >= s->num_irq) {
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goto bad_reg;
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}
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@ -1375,7 +1372,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
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}
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} else if (offset < 0xf00) {
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
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irq = (offset - 0xc00) * 4;
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if (irq >= s->num_irq)
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goto bad_reg;
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if (irq < GIC_NR_SGIS)
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@ -191,7 +191,6 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
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s->num_cpu, GIC_NCPU);
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return;
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}
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s->num_irq += GIC_BASE_IRQ;
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if (s->num_irq > GIC_MAXIRQ) {
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error_setg(errp,
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"requested %u interrupt lines exceeds GIC maximum %d",
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@ -26,8 +26,6 @@
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#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
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#define GIC_BASE_IRQ 0
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#define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))
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#define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm))
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#define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
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