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https://gitlab.com/qemu-project/qemu
synced 2024-09-06 18:05:37 +00:00
8250: Customized base baudrate
(Jan Kiszka) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4336 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
6936bfe514
commit
b6cd0ea120
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@ -234,9 +234,9 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
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/* Serial ports */
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if (serial_hds[0])
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serial_mm_init(0x80006000, 0, rc4030[8], serial_hds[0], 1);
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serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
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if (serial_hds[1])
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serial_mm_init(0x80007000, 0, rc4030[9], serial_hds[1], 1);
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serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
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/* Parallel port */
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if (parallel_hds[0])
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@ -449,7 +449,8 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
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uart_chr = qemu_chr_open("vc:80Cx24C");
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qemu_chr_printf(uart_chr, "CBUS UART\r\n");
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s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
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s->uart =
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serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);
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malta_fpga_reset(s);
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qemu_register_reset(malta_fpga_reset, s);
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@ -918,9 +919,9 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
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i8042_init(i8259[1], i8259[12], 0x60);
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rtc_state = rtc_init(0x70, i8259[8]);
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if (serial_hds[0])
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serial_init(0x3f8, i8259[4], serial_hds[0]);
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serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
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if (serial_hds[1])
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serial_init(0x2f8, i8259[3], serial_hds[1]);
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serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
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if (parallel_hds[0])
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parallel_init(0x378, i8259[7], parallel_hds[0]);
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for(i = 0; i < MAX_FD; i++) {
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@ -174,7 +174,7 @@ mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
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/* A single 16450 sits at offset 0x3f8. It is attached to
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MIPS CPU INT2, which is interrupt 4. */
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if (serial_hds[0])
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serial_init(0x3f8, env->irq[4], serial_hds[0]);
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serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]);
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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@ -241,7 +241,8 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
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serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
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serial_hds[i]);
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}
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}
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@ -1448,10 +1448,10 @@ static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
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mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
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if (serial_hds[0])
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serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], /*1825000,*/
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serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
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serial_hds[0], 1);
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if (serial_hds[1])
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serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], /*1825000,*/
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serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
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serial_hds[1], 1);
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/* Register flash */
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@ -2006,7 +2006,8 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
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struct omap_uart_s *s = (struct omap_uart_s *)
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qemu_mallocz(sizeof(struct omap_uart_s));
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s->serial = serial_mm_init(base, 2, irq, chr ?: qemu_chr_open("null"), 1);
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s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
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chr ?: qemu_chr_open("null"), 1);
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return s;
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}
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3
hw/pc.c
3
hw/pc.c
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@ -930,7 +930,8 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
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serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
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serial_hds[i]);
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}
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}
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7
hw/pc.h
7
hw/pc.h
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@ -4,10 +4,11 @@
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/* serial.c */
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SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
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SerialState *serial_init(int base, qemu_irq irq, int baudbase,
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CharDriverState *chr);
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SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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qemu_irq irq, CharDriverState *chr,
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int ioregister);
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qemu_irq irq, int baudbase,
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CharDriverState *chr, int ioregister);
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uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
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void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
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uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
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@ -1223,7 +1223,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
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#ifdef DEBUG_SERIAL
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printf("%s: offset " PADDRX "\n", __func__, offset);
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#endif
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serial = serial_mm_init(offset, 0, irq, chr, 0);
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serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
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ppc4xx_mmio_register(env, mmio, offset, 0x008,
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serial_mm_read, serial_mm_write, serial);
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}
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@ -264,7 +264,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
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dummy_irq = i8259_init(NULL);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
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serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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if (!nd_table[i].model)
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nd_table[i].model = "ne2k_pci";
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@ -287,7 +287,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
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dummy_irq = i8259_init(NULL);
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/* XXX: use Mac Serial port */
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serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
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serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
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for(i = 0; i < nb_nics; i++) {
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if (!nd_table[i].model)
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@ -667,7 +667,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
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// pit = pit_init(0x40, i8259[0]);
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rtc_init(0x70, i8259[8]);
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serial_init(0x3f8, i8259[4], serial_hds[0]);
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serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
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nb_nics1 = nb_nics;
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if (nb_nics1 > NE2000_NB_MAX)
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nb_nics1 = NE2000_NB_MAX;
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@ -2077,7 +2077,8 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
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for (i = 0; pxa270_serial[i].io_base; i ++)
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if (serial_hds[i])
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serial_mm_init(pxa270_serial[i].io_base, 2,
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s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
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s->pic[pxa270_serial[i].irqn], 14857000/16,
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serial_hds[i], 1);
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else
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break;
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if (serial_hds[i])
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@ -2202,7 +2203,8 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
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for (i = 0; pxa255_serial[i].io_base; i ++)
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if (serial_hds[i])
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serial_mm_init(pxa255_serial[i].io_base, 2,
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s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
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s->pic[pxa255_serial[i].irqn], 14745600/16,
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serial_hds[i], 1);
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else
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break;
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if (serial_hds[i])
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14
hw/serial.c
14
hw/serial.c
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@ -99,6 +99,7 @@ struct SerialState {
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int last_break_enable;
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target_phys_addr_t base;
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int it_shift;
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int baudbase;
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QEMUTimer *tx_timer;
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int tx_burst;
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};
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@ -135,7 +136,7 @@ static void serial_tx_done(void *opaque)
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/* We assume 10 bits/char, OK for this purpose. */
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s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
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(1000000 * 10 / (115200 / divider));
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(1000000 * 10 / (s->baudbase / divider));
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}
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s->thr_ipending = 1;
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s->lsr |= UART_LSR_THRE;
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@ -163,7 +164,7 @@ static void serial_update_parameters(SerialState *s)
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data_bits = (s->lcr & 0x03) + 5;
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if (s->divider == 0)
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return;
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speed = 115200 / s->divider;
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speed = s->baudbase / s->divider;
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ssp.speed = speed;
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ssp.parity = parity;
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ssp.data_bits = data_bits;
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}
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/* If fd is zero, it means that the serial device uses the console */
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SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
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SerialState *serial_init(int base, qemu_irq irq, int baudbase,
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CharDriverState *chr)
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{
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SerialState *s;
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@ -421,6 +423,7 @@ SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
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if (!s)
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return NULL;
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s->irq = irq;
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s->baudbase = baudbase;
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s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
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if (!s->tx_timer)
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@ -512,8 +515,8 @@ static CPUWriteMemoryFunc *serial_mm_write[] = {
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};
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SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
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qemu_irq irq, CharDriverState *chr,
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int ioregister)
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qemu_irq irq, int baudbase,
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CharDriverState *chr, int ioregister)
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{
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SerialState *s;
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int s_io_memory;
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s->irq = irq;
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s->base = base;
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s->it_shift = it_shift;
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s->baudbase= baudbase;
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s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
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if (!s->tx_timer)
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