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https://gitlab.com/qemu-project/qemu
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tcg-ia64: Move bswap for store into tlb load
Saving at least two cycles per store, and cleaning up the code. Signed-off-by: Richard Henderson <rth@twiddle.net>
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4c186ee2cf
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b672cf66c3
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@ -1571,9 +1571,11 @@ QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])
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/* Load and compare a TLB entry, and return the result in (p6, p7).
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R2 is loaded with the address of the addend TLB entry.
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R57 is loaded with the address, zero extented on 32-bit targets.
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R1, R3 are clobbered. */
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R1, R3 are clobbered, leaving R56 free for...
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BSWAP_1, BSWAP_2 and I-slot insns for swapping data for store. */
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static inline void tcg_out_qemu_tlb(TCGContext *s, TCGReg addr_reg,
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TCGMemOp s_bits, int off_rw, int off_add)
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TCGMemOp s_bits, int off_rw, int off_add,
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uint64_t bswap1, uint64_t bswap2)
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{
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/*
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.mii
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@ -1621,12 +1623,12 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGReg addr_reg,
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(TARGET_LONG_BITS == 32
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? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R3,
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TCG_REG_R2, off_add - off_rw),
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INSN_NOP_I);
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bswap1);
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tcg_out_bundle(s, mmI,
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INSN_NOP_M,
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tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
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TCG_REG_P7, TCG_REG_R1, TCG_REG_R3),
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INSN_NOP_I);
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bswap2);
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}
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/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
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@ -1656,7 +1658,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
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/* Read the TLB entry */
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tcg_out_qemu_tlb(s, addr_reg, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
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offsetof(CPUArchState, tlb_table[mem_index][0].addend));
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offsetof(CPUArchState, tlb_table[mem_index][0].addend),
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INSN_NOP_I, INSN_NOP_I);
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/* P6 is the fast path, and P7 the slow path */
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tcg_out_bundle(s, mLX,
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@ -1727,17 +1730,31 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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static const uint64_t opc_st_m4[4] = {
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OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
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};
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int addr_reg, data_reg, mem_index;
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TCGReg addr_reg, data_reg, store_reg;
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int mem_index;
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uint64_t bswap1, bswap2;
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TCGMemOp s_bits;
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data_reg = *args++;
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store_reg = data_reg = *args++;
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addr_reg = *args++;
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mem_index = *args;
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s_bits = opc & MO_SIZE;
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bswap1 = bswap2 = INSN_NOP_I;
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if (opc & MO_BSWAP) {
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store_reg = TCG_REG_R56;
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bswap1 = tcg_opc_bswap64_i(TCG_REG_P0, store_reg, data_reg);
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if (s_bits < MO_64) {
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int shift = 64 - (8 << s_bits);
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bswap2 = tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11,
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store_reg, store_reg, shift, 63 - shift);
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}
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}
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tcg_out_qemu_tlb(s, addr_reg, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
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offsetof(CPUArchState, tlb_table[mem_index][0].addend));
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offsetof(CPUArchState, tlb_table[mem_index][0].addend),
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bswap1, bswap2);
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/* P6 is the fast path, and P7 the slow path */
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tcg_out_bundle(s, mLX,
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@ -1752,63 +1769,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
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TCG_REG_R3, TCG_REG_R57),
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tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
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TCG_REG_R3, 0));
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switch (opc) {
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case MO_8:
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case MO_16:
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case MO_32:
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case MO_64:
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tcg_out_bundle(s, mii,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
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INSN_NOP_I);
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break;
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case MO_16 | MO_BSWAP:
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tcg_out_bundle(s, miI,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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INSN_NOP_I,
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tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
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TCG_REG_R2, data_reg, 15, 15));
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tcg_out_bundle(s, miI,
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tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
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INSN_NOP_I,
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tcg_opc_bswap64_i(TCG_REG_P6, TCG_REG_R2, TCG_REG_R2));
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data_reg = TCG_REG_R2;
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break;
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case MO_32 | MO_BSWAP:
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tcg_out_bundle(s, miI,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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INSN_NOP_I,
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tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
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TCG_REG_R2, data_reg, 31, 31));
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tcg_out_bundle(s, miI,
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tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
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INSN_NOP_I,
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tcg_opc_bswap64_i(TCG_REG_P6, TCG_REG_R2, TCG_REG_R2));
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data_reg = TCG_REG_R2;
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break;
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case MO_64 | MO_BSWAP:
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tcg_out_bundle(s, miI,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
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tcg_opc_bswap64_i(TCG_REG_P6, TCG_REG_R2, data_reg));
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data_reg = TCG_REG_R2;
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break;
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default:
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tcg_abort();
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}
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tcg_out_bundle(s, mii,
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tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
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TCG_REG_R1, TCG_REG_R2),
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tcg_opc_mov_a(TCG_REG_P7, TCG_REG_R58, data_reg),
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INSN_NOP_I);
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tcg_out_bundle(s, miB,
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tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
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data_reg, TCG_REG_R3),
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store_reg, TCG_REG_R3),
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tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R59, mem_index),
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tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
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TCG_REG_B0, TCG_REG_B6));
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