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https://gitlab.com/qemu-project/qemu
synced 2024-10-14 23:13:30 +00:00
target/microblaze: Drop tcg_temp_free
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
446914b7b7
commit
b304346e8b
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@ -104,7 +104,6 @@ static void gen_raise_exception(DisasContext *dc, uint32_t index)
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TCGv_i32 tmp = tcg_const_i32(index);
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gen_helper_raise_exception(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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dc->base.is_jmp = DISAS_NORETURN;
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}
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@ -119,7 +118,6 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
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{
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TCGv_i32 tmp = tcg_const_i32(esr_ec);
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tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr));
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tcg_temp_free_i32(tmp);
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gen_raise_exception_sync(dc, EXCP_HW_EXCP);
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}
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@ -265,8 +263,6 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects,
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imm = tcg_const_i32(arg->imm);
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fn(rd, ra, imm);
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tcg_temp_free_i32(imm);
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return true;
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}
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@ -312,8 +308,6 @@ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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TCGv_i32 zero = tcg_const_i32(0);
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tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero);
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tcg_temp_free_i32(zero);
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}
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/* Input and output carry. */
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@ -324,9 +318,6 @@ static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero);
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tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(zero);
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}
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/* Input carry, but no output carry. */
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@ -361,7 +352,6 @@ static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_andi_i32(tmp, inb, 31);
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tcg_gen_sar_i32(out, ina, tmp);
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tcg_temp_free_i32(tmp);
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}
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static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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@ -369,7 +359,6 @@ static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_andi_i32(tmp, inb, 31);
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tcg_gen_shr_i32(out, ina, tmp);
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tcg_temp_free_i32(tmp);
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}
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static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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@ -377,7 +366,6 @@ static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_andi_i32(tmp, inb, 31);
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tcg_gen_shl_i32(out, ina, tmp);
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tcg_temp_free_i32(tmp);
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}
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static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm)
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@ -436,7 +424,6 @@ static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina);
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tcg_gen_sub_i32(out, inb, ina);
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tcg_gen_deposit_i32(out, out, lt, 31, 1);
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tcg_temp_free_i32(lt);
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}
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static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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@ -446,7 +433,6 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina);
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tcg_gen_sub_i32(out, inb, ina);
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tcg_gen_deposit_i32(out, out, lt, 31, 1);
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tcg_temp_free_i32(lt);
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}
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DO_TYPEA(cmp, false, gen_cmp)
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@ -513,21 +499,18 @@ static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_muls2_i32(tmp, out, ina, inb);
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tcg_temp_free_i32(tmp);
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}
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static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_mulu2_i32(tmp, out, ina, inb);
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tcg_temp_free_i32(tmp);
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}
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static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_mulsu2_i32(tmp, out, ina, inb);
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tcg_temp_free_i32(tmp);
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}
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DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32)
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@ -569,9 +552,6 @@ static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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tcg_gen_not_i32(tmp, ina);
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tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero);
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tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
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tcg_temp_free_i32(zero);
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tcg_temp_free_i32(tmp);
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}
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/* No input or output carry. */
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@ -588,8 +568,6 @@ static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
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tcg_gen_not_i32(nota, ina);
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tcg_gen_add_i32(out, inb, nota);
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tcg_gen_add_i32(out, out, cpu_msr_c);
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tcg_temp_free_i32(nota);
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}
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DO_TYPEA(rsub, true, gen_rsub)
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@ -618,8 +596,6 @@ static void gen_src(TCGv_i32 out, TCGv_i32 ina)
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tcg_gen_mov_i32(tmp, cpu_msr_c);
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tcg_gen_andi_i32(cpu_msr_c, ina, 1);
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tcg_gen_extract2_i32(out, ina, tmp, 1);
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tcg_temp_free_i32(tmp);
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}
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static void gen_srl(TCGv_i32 out, TCGv_i32 ina)
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@ -659,7 +635,6 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
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tcg_gen_extu_i32_tl(ret, tmp);
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tcg_temp_free_i32(tmp);
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} else if (ra) {
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tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
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} else if (rb) {
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@ -683,7 +658,6 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
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tcg_gen_extu_i32_tl(ret, tmp);
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tcg_temp_free_i32(tmp);
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} else {
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tcg_gen_movi_tl(ret, (uint32_t)imm);
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}
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@ -772,8 +746,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
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#endif
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tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop);
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tcg_temp_free(addr);
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return true;
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}
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@ -879,7 +851,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
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tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
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tcg_gen_mov_tl(cpu_res_addr, addr);
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tcg_temp_free(addr);
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if (arg->rd) {
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tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
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@ -925,8 +896,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
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#endif
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tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);
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tcg_temp_free(addr);
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return true;
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}
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@ -1040,7 +1009,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
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* In either case, addr is no longer needed.
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*/
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tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
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tcg_temp_free(addr);
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/*
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* Compare the value loaded during lwx with current contents of
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@ -1053,7 +1021,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
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dc->mem_index, MO_TEUL);
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tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
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tcg_temp_free_i32(tval);
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/* Success */
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tcg_gen_movi_i32(cpu_msr_c, 0);
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@ -1155,8 +1122,6 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm,
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tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget,
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reg_for_read(dc, ra), zero,
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cpu_btarget, next);
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tcg_temp_free_i32(zero);
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tcg_temp_free_i32(next);
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return true;
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}
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@ -1274,7 +1239,6 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *arg)
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tcg_gen_st_i32(tmp_1, cpu_env,
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-offsetof(MicroBlazeCPU, env)
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+offsetof(CPUState, halted));
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tcg_temp_free_i32(tmp_1);
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tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
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@ -1345,7 +1309,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d)
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t = tcg_temp_new_i32();
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tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC);
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tcg_gen_or_i32(d, cpu_msr, t);
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tcg_temp_free_i32(t);
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}
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static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
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@ -1442,8 +1405,6 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
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TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
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gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src);
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tcg_temp_free_i32(tmp_reg);
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tcg_temp_free_i32(tmp_ext);
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}
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break;
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@ -1467,7 +1428,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
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TCGv_i64 t64 = tcg_temp_new_i64();
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tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
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tcg_gen_extrh_i64_i32(dest, t64);
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tcg_temp_free_i64(t64);
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}
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return true;
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#ifndef CONFIG_USER_ONLY
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@ -1498,7 +1458,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
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TCGv_i64 t64 = tcg_temp_new_i64();
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tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
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tcg_gen_extrl_i64_i32(dest, t64);
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tcg_temp_free_i64(t64);
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}
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break;
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case SR_ESR:
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@ -1532,8 +1491,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
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TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
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gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg);
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tcg_temp_free_i32(tmp_reg);
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tcg_temp_free_i32(tmp_ext);
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}
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break;
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#endif
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@ -1559,8 +1516,6 @@ static void do_rti(DisasContext *dc)
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tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM);
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tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM));
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tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
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tcg_temp_free_i32(tmp);
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}
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static void do_rtb(DisasContext *dc)
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@ -1571,8 +1526,6 @@ static void do_rtb(DisasContext *dc)
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tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP));
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tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
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tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
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tcg_temp_free_i32(tmp);
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}
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static void do_rte(DisasContext *dc)
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@ -1584,8 +1537,6 @@ static void do_rte(DisasContext *dc)
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tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
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tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP));
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tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
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tcg_temp_free_i32(tmp);
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}
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/* Insns connected to FSL or AXI stream attached devices. */
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@ -1606,8 +1557,6 @@ static bool do_get(DisasContext *dc, int rd, int rb, int imm, int ctrl)
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t_ctrl = tcg_const_i32(ctrl);
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gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl);
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tcg_temp_free_i32(t_id);
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tcg_temp_free_i32(t_ctrl);
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return true;
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}
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@ -1638,8 +1587,6 @@ static bool do_put(DisasContext *dc, int ra, int rb, int imm, int ctrl)
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t_ctrl = tcg_const_i32(ctrl);
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gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra));
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tcg_temp_free_i32(t_id);
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tcg_temp_free_i32(t_ctrl);
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return true;
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}
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@ -1704,7 +1651,6 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
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}
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if (dc->r0) {
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tcg_temp_free_i32(dc->r0);
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dc->r0 = NULL;
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dc->r0_set = false;
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}
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